High-electron-mobility transistor with buried interconnect

• US 10,381,473 B2
• Filed: 07/06/2017
• Issued: 08/13/2019
• Est. Priority Date: 12/02/2016
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Shibib, Ayman, Terrill, Kyle, Ding, Yongping, Yang, Jinman
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/643,328
• Publication Number:
  US 20180158942A1
• Time in Patent Office: 768 Days
• Field of Search: 257190, 257192, 257194
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42312 Gate electrodes for field effect devices
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.

Claims

1. An electronic device comprising a high-electron-mobility transistor (HEMT), wherein the HEMT comprises:

a substrate layer comprising silicon;

a first contact disposed on a first surface of the substrate layer;

a plurality of layers disposed on a second surface of the substrate layer, wherein the second surface is opposite the first surface;

a second contact and a gate contact disposed on the plurality of layers;

a trench comprising conducting material that extends through the plurality of layers and into the substrate layer; and

an insulating layer disposed between the conducting material and sidewalls of the trench, wherein the conducting material in the trench is in contact with the substrate layer through an opening in the insulating layer,

wherein the gate contact comprises a region that comprises gallium that is doped to p-type, and wherein the plurality of layers comprises;

a buffer layer adjacent to the substrate layer;

a first layer comprising gallium adjacent to the buffer layer;

a two-dimensional electron gas (2DEG) layer adjacent to the first layer comprising gallium; and

a second layer comprising gallium adjacent to the 2DEG layer, wherein the conducting material in the trench is in contact with the second layer and the 2DEG layer, wherein the first layer is in contact with the second layer through an opening in the 2DEG layer, and wherein the opening is aligned with the gate contact.

2. The electronic device of claim 1, wherein the first contact comprises a source contact and wherein the second contact comprises a drain contact.

3. The electronic device of claim 2, wherein the HEMT further comprises a spacer comprising an insulating material disposed on the plurality of layers between the gate contact and the trench.

4. The electronic device of claim 2, further comprising:

a passivation layer disposed on the plurality of layers and around the gate contact and the second contact;

a first field plate disposed within the passivation layer, wherein the gate contact is separated from the first field plate by a region of the passivation layer; and

a second field plate disposed within the passivation layer and connected to the drain contact.

5. The electronic device of claim 1, wherein the first contact comprises a drain contact and wherein the second contact comprises a source contact.

6. The electronic device of claim 5, further comprising:

a passivation layer disposed on the plurality of layers and around the gate contact; and

a field plate disposed within the passivation layer and connected to the source contact, wherein the gate contact is separated from the field plate by a region of the passivation layer.

7. The electronic device of claim 1, wherein the first layer comprises gallium nitride (GaN) and the second layer comprises aluminum gallium nitride (AlGaN), and wherein the buffer layer comprises aluminum nitride and alternating layers of GaN and AlGaN.

8. The electronic device of claim 1, wherein the silicon in the substrate layer has a resistivity that does not exceed one milliohm-centimeter.

9. An electronic device comprising a field effect transistor (FET), wherein the FET comprises:

a substrate layer comprising silicon;

a first contact disposed on a first surface of the substrate layer;

a buffer layer disposed on a second surface of the substrate layer, wherein the second surface is opposite the first surface;

a first layer comprising gallium adjacent to the buffer layer;

a two-dimensional electron gas (2DEG) layer adjacent to the first layer comprising gallium;

a second layer comprising gallium adjacent to the 2DEG layer;

a second contact and a gate contact disposed on the second layer, wherein the first layer is in contact with the second layer through an opening in the 2DEG layer, and wherein the opening is aligned with the gate contact; and

a trench comprising conducting material that extends completely through the second layer, the 2DEG layer, the first layer, and the buffer layer and into the substrate layer, wherein the trench further comprises an insulating layer disposed between the conducting material and the first layer, the buffer layer, and substrate layer, wherein the conducting material in the trench is in contact with the substrate layer through an opening in the insulating layer, and wherein the conducting material in the trench is in contact with the second layer and the 2DEG layer.

10. The electronic device of claim 9, wherein the first contact comprises a source contact and wherein the second contact comprises a drain contact, wherein the FET further comprises a spacer comprising an insulating material disposed on the second layer between the gate contact and the trench.

11. The electronic device of claim 10, further comprising:

a passivation layer disposed on the second layer and around the gate contact and the second contact;

a first field plate disposed within the passivation layer, wherein the gate contact is separated from the first field plate by a region of the passivation layer; and

a second field plate disposed within the passivation layer and connected to the drain contact.

12. The electronic device of claim 9, wherein the first contact comprises a drain contact and wherein the second contact comprises a source contact.

13. The electronic device of claim 12, further comprising:

a passivation layer disposed on the second layer and around the gate contact;

a metal interconnect; and

a field plate disposed within the passivation layer, wherein the gate contact is separated from the field plate by a region of the passivation layer, and wherein the metal interconnect extends from the source contact and the field plate is connected to the metal interconnect.

14. The electronic device of claim 9, wherein the opening is aligned with the gate contact.

15. The electronic device of claim 9, wherein the first layer comprises gallium nitride (GaN) and the second layer comprises aluminum gallium nitride (AlGaN), and wherein the buffer layer comprises aluminum nitride and alternating layers of GaN and AlGaN.