Interface charge reduction for SiGe surface

• US 10,381,479 B2
• Filed: 07/28/2017
• Issued: 08/13/2019
• Est. Priority Date: 07/28/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sadana, Devendra, Guo, Dechao, de Souza, Joel P., Bao, Ruqiang, Bedell, Stephen W., Mochizuki, Shogo, Tsutsui, Gen, Jagannathan, Hemanth, Hopstaken, Marinus
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/663,133
• Publication Number:
  US 20190035923A1
• Time in Patent Office: 746 Days
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

Claims

1. A method for reducing interface charge density (Dit) for a silicon germanium (SiGe) channel material, the method comprising the steps of:

contacting the SiGe channel material with an n-dopant precursor under conditions sufficient to chemically dope a surface of the SiGe channel material with an n-type dopant;

contacting the SiGe channel material with a silicon (Si)-containing chemical precursor under conditions sufficient to form a thin continuous Si layer on a surface of the SiGe channel material, wherein the SiGe channel material is contacted with the n-dopant precursor prior to contacting the SiGe channel material with the Si-containing chemical precursor; and

depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit.

2. The method of claim 1, wherein the thin continuous Si layer is less than 5 monolayers thick.

3. The method of claim 1, further comprising the step of:

epitaxially growing the SiGe channel material on a substrate.

4. The method of claim 1, wherein the conditions sufficient to form the thin continuous Si layer on the surface of the SiGe channel material comprise a temperature, a pressure and a duration.

5. The method of claim 4, wherein the temperature is from about 400°

C. to about 800°

C. and ranges therebetween, the pressure is from about 1 torr to about 100 torr and ranges therebetween, and the duration of from about 1 second to about 100 seconds and ranges therebetween.

6. The method of claim 1, wherein the Si-containing chemical precursor is in a solid, a liquid or a gaseous form.

7. The method of claim 1, wherein the Si-containing chemical precursor is selected from the group consisting of:

silane, disilane, and dichlorosilane.

8. The method of claim 1, wherein the Si-containing chemical precursor is dichlorosilane.

9. The method of claim 8, wherein a temperature ramp up of from about 2°

C./second to about 4°

C./second and ranges therebetween, is employed.

10. The method of claim 1, wherein the conditions sufficient to chemically dope the surface of the SiGe channel material with the n-type dopant comprise a temperature, a pressure and a duration.

11. The method of claim 10, wherein the temperature is from about 400°

C. to about 700°

C. and ranges therebetween, the pressure is from about 1 torr to about 100 torr and ranges therebetween, and the duration of from about 1 second to about 100 seconds and ranges therebetween.

12. The method of claim 1, further comprising the step of:

diluting the n-dopant precursor with a carrier gas to achieve a desired n-dopant surface concentration on the SiGe channel material.

13. The method of claim 12, wherein the desired n-dopant surface concentration on the SiGe channel material is from about 1×

10¹⁹ cm<sup>−

3</sup> to about 3×

10²¹ cm<sup>−

3</sup> and ranges therebetween.

14. The method of claim 1, wherein the n-dopant precursor is selected from the group consisting of:

tributyl phosphate and phosphine.

15. The method of claim 1, wherein the SiGe channel material comprises planar surfaces and faceted surfaces, wherein the Si monolayer has a thickness T1 over the planar surfaces and a thickness T2 over the faceted surfaces, and wherein T1>

T2.

16. A method of forming a field effect transistor (FET) device, the method comprising the steps of:

epitaxially growing a SiGe channel material on a substrate;

contacting the SiGe channel material with an n-dopant precursor under conditions sufficient to chemically dope a surface of the SiGe channel material with an n-type dopant;

contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer on a surface of the SiGe channel material, wherein the SiGe channel material is contacted with the n-dopant precursor prior to contacting the SiGe channel material with the Si-containing chemical precursor;

forming a gate stack on the SiGe channel material, wherein the gate stack comprises a gate dielectric on the SiGe channel material over the thin continuous Si layer and a gate conductor on the gate dielectric, and wherein the thin continuous Si layer passivates an interface between the SiGe channel material and the gate dielectric.

17. The method of claim 16, wherein the thin continuous Si layer is less than 5 monolayers thick.

18. The method of claim 16, further comprising the steps of:

patterning the SiGe channel material and the substrate into at least one fin with each fin having a top portion comprising the SiGe material and a bottom portion comprising the substrate; and

depositing a shallow trench isolation (STI) oxide around the bottom portion of each fin.

19. The method of claim 16, further comprising the steps of:

forming a dummy gate over the SiGe channel material;

forming spacers on opposite sides of the dummy gate;

forming source and drain regions offset from the dummy gate by the spacers;

depositing a dielectric material around the dummy gate;

removing the dummy gate selective to the dielectric material so as to form a gate trench in the dielectric;

after removal of the dummy gate, contacting the SiGe channel material with the Si-containing chemical precursor under conditions sufficient to form the thin continuous Si layer on the SiGe channel material within the gate trench; and

replacing the dummy gate with the gate stack.

20. The method of claim 16, further comprising the steps of:

forming a dummy gate over SiGe channel material after the thin continuous Si layer has been formed on the surface of the SiGe channel material;

forming spacers on opposite sides of the dummy gate;

forming source and drain regions offset from the dummy gate by the spacers;

depositing a dielectric material around the dummy gate;

removing the dummy gate selective to the dielectric material so as to form a gate trench in the dielectric; and

replacing the dummy gate with the gate stack.