Method and system for engineering the secondary barrier layer in dual magnetic junctions

• US 10,381,550 B1
• Filed: 05/01/2018
• Issued: 08/13/2019
• Est. Priority Date: 03/01/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Duan, Zheng, Apalkov, Dmytro, Nikitin, Vladimir
• Primary Examiner(s): Sefer, Ahmed N
• Application Number:
  US15/968,471
• Publication Number:
  US 20190273201A1
• Time in Patent Office: 469 Days
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes first and second reference layers, a main barrier layer having a first thickness, a free layer, an engineered secondary barrier layer and a second reference layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The main barrier layer is between the first reference layer and the free layer. The secondary barrier layer is between the free layer and the second reference layer. The engineered secondary barrier layer has a resistance, a second thickness less than the first thickness and a plurality of regions having a reduced resistance less than the resistance. The free and reference layers each has a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.

Claims

1. A magnetic junction residing on a substrate and usable in a magnetic device, the magnetic junction comprising:

a first reference layer;

a main barrier layer having a first thickness;

a free layer, the free layer being switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction, the main barrier layer residing between the first reference layer and the free layer;

an engineered secondary barrier layer having a second thickness less than the first thickness, the engineered secondary barrier layer having a plurality of regions having a reduced resistance less than a resistance of the secondary barrier layer; and

a second reference layer, the secondary barrier layer being between the free layer and the second reference layer, each of the free layer, the first reference layer and the second reference layer having a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.

2. The magnetic junction of claim 1 wherein the first reference layer and the second reference layer are in a dual state.

3. The magnetic junction of claim 1 wherein each of the plurality of regions has a reduced thickness less than the second thickness.

4. The magnetic junction of claim 1 wherein the engineered secondary barrier layer includes not more than five atomic percent of at least one metallic dopant, the plurality of regions being dopant rich.

5. The magnetic junction of claim 4 wherein the dopant includes at least one of Fe, Ni, Cr, Ti and Mg.

6. The magnetic junction of claim 1 wherein the engineered secondary barrier layer includes an insulator intermixed with at least one conductor, the plurality of regions being rich in the at least one conductor.

7. The magnetic junction of claim 6 wherein the at least one conductor includes at least one of Fe, Ni, Cr, Ti and Mg.

8. The magnetic junction of claim 1 wherein the engineered secondary barrier layer has a first resistance area product (RA) and consists of at least one material, the first RA being less than a second RA of a nonengineered secondary barrier layer having the second thickness, consisting of the at least one material and being free of the plurality of regions.

9. The magnetic junction of claim 8 wherein the main barrier layer and the secondary barrier layer each include at least one of magnesium oxide, magnesium aluminum oxide, magnesium titanium oxide and magnesium iron oxide.

10. The magnetic junction of claim 1 wherein magnetic junction has a first tunneling magnetoresistance (TMR), the first TMR being greater than a second TMR of another magnetic junction including the first reference layer, the main barrier layer, the free layer, the second reference layer and a nonengineered secondary barrier layer having the second thickness, consisting of the at least one material and being free of the plurality of regions.

11. A magnetic memory residing on a substrate and comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic junction, each of the at least one magnetic junction including a first reference layer, a main barrier layer having a first thickness, a free layer, an engineered secondary barrier layer and a second reference layer, the free layer being switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction, the main barrier layer residing between the first reference layer and the free layer, the engineered secondary barrier layer having a second thickness less than the first thickness, the engineered secondary barrier layer having a plurality of regions having a reduced resistance less than a resistance of the secondary barrier layer, the secondary barrier layer being between the free layer and the second reference layer, each of the free layer, the first reference layer and the second reference layer having a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy; and

a plurality of bit lines coupled with the plurality of magnetic storage cells.

12. A method for providing a magnetic junction usable in a magnetic device, the method comprising:

providing a first reference layer;

providing a main barrier layer having a first thickness;

providing a free layer, the free layer being switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction, the main barrier layer residing between the first reference layer and the free layer;

providing an engineered secondary barrier layer having a second thickness less than the first thickness, the engineered secondary barrier layer having a plurality of regions having a reduced resistance less than a resistance of the secondary barrier layer;

providing a second reference layer, the secondary barrier layer being between the free layer and the second reference layer, each of the free layer, the first reference layer and the second reference layer having a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.

13. The method of claim 12 wherein the first reference layer and the second reference layer are in a dual state.

14. The method of claim 12 wherein each of the plurality of regions has a reduced thickness less than the second thickness.

15. The method of claim 14 wherein the step of providing the engineered secondary barrier layer further includes:

providing the engineered secondary barrier layer such that the plurality of regions has a zero thickness.

16. The method of claim 14 wherein the step of providing the engineered secondary barrier layer further includes:

doping the engineered secondary barrier layer with not more than five atomic percent of at least one metallic dopant, the plurality of regions being dopant rich.

17. The method of claim 12 wherein the engineered secondary barrier layer includes an insulator intermixed with at least one conductor, the plurality of regions being rich in the at least one conductor.

18. The method of claim 17 wherein the step of providing the engineered secondary barrier layer includes:

depositing a layer consisting of the insulator;

depositing at least one layer consisting of the at least one conductor; and

annealing the layer and the at least one layer to intermix the insulator with the at least one conductor.