Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

• US 10,382,016 B2
• Filed: 03/26/2015
• Issued: 08/13/2019
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US14/669,670
• Publication Number:
  US 20150200657A1
• Time in Patent Office: 1,601 Days
• Field of Search: None
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Claims

1. A semiconductor device comprising:

a first element;

a second element;

an insulating layer over the first element and the second element; and

a data holding portion comprising a transistor and a capacitor,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element,

wherein each of the first element and the second element comprises a transistor whose channel formation region includes crystalline silicon,

wherein a channel formation region of the transistor of the data holding portion includes an oxide semiconductor layer over the insulating layer,

wherein one of a source and a drain of the transistor of the data holding portion is electrically connected to one of a pair of electrodes of the capacitor, and

wherein the other of the source and the drain of the transistor of the data holding portion is electrically connected to the input of the first element and a wiring supplied with an input signal.

2. The semiconductor device according to claim 1, further comprising a first switch and a second switch,

wherein the output of the second element is electrically connected to the input of the first element through the second switch, and

wherein the input of the first element is electrically connected to the wiring supplied with the input signal through the first switch.

3. The semiconductor device according to claim 1, wherein the first element is an inverter and the second element is an inverter.

4. The semiconductor device according to claim 1, wherein the first element is a NAND and the second element is a clocked inverter.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises crystals whose c-axes are substantially perpendicular to a surface of the oxide semiconductor layer.

7. A logic circuit including the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a first element;

a second element;

an insulating layer over the first element and the second element; and

a data holding portion comprising a first transistor, a second transistor, a first capacitor and a second capacitor,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element,

wherein each of the first element and the second element comprises a transistor whose channel formation region includes crystalline silicon,

wherein a channel formation region of each of the first transistor and the second transistor includes an oxide semiconductor layer over the insulating layer,

wherein one of a source and a drain of the first transistor is electrically connected to one of a pair of electrodes of the first capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a pair of electrodes of the second capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to the input of the first element, and

wherein the other of the source and the drain of the second transistor is electrically connected to the output of the first element.

9. The semiconductor device according to claim 8, further comprising a first switch and a second switch,

wherein the output of the second element is electrically connected to the input of the first element through the second switch, and

wherein the input of the first element is electrically connected to a wiring supplied with an input signal through the first switch.

10. The semiconductor device according to claim 8, wherein the first element is an inverter and the second element is an inverter.

11. The semiconductor device according to claim 8, wherein the first element is a NAND and the second element is a clocked inverter.

12. The semiconductor device according to claim 8, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

13. The semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises crystals whose c-axes are substantially perpendicular to a surface of the oxide semiconductor layer.

14. A logic circuit including the semiconductor device according to claim 8.

15. A CPU including the logic circuit according to claim 8.

16. A semiconductor device comprising:

a first element;

a second element;

an insulating layer over the first element and the second element; and

a data holding portion comprising a transistor and a capacitor,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element,

wherein each of the first element and the second element comprises a transistor whose channel formation region is in a crystalline silicon substrate,

wherein a channel formation region of the transistor of the data holding portion includes an oxide semiconductor layer over the insulating layer,

wherein one of a source and a drain of the transistor of the data holding portion is electrically connected to one of a pair of electrodes of the capacitor, and

wherein the other of the source and the drain of the transistor of the data holding portion is electrically connected to the input of the first element and a wiring supplied with an input signal.

17. The semiconductor device according to claim 16, further comprising a first switch and a second switch,

wherein the output of the second element is electrically connected to the input of the first element through the second switch, and

wherein the input of the first element is electrically connected to the wiring supplied with the input signal through the first switch.

18. The semiconductor device according to claim 16, wherein the first element is an inverter and the second element is an inverter.

19. The semiconductor device according to claim 16, wherein the first element is a NAND and the second element is a clocked inverter.

20. The semiconductor device according to claim 16, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

21. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises a crystal whose c-axis is substantially perpendicular to a surface of the oxide semiconductor layer.

22. A logic circuit including the semiconductor device according to claim 16.