Power management integrated circuit, power management method, mobile device and clock adjusting method

• US 10,383,062 B2
• Filed: 07/07/2015
• Issued: 08/13/2019
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Heo, Junghun, Kim, Youngduk, Kim, Joonseok, Shin, Dongsuk
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Pandey, Keshab R
• Application Number:
  US14/793,381
• Publication Number:
  US 20160066280A1
• Time in Patent Office: 1,498 Days
• Field of Search: 713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713345, 713375
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: H04W 52/0261 managing power supply demand, e.g. depending on battery level
• CPC Class Codes: H04W 52/0287 changing the clock frequency of a controller in the equipment
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

Claims

1. A power management method for a mobile device including a battery providing a power supply voltage, a system-on-chip (SoC) including a central processing unit (CPU) operating in response to an operating clock, and a power management integrated circuit (PMIC) separate from the SoC and receiving the power supply voltage from the battery, the method comprising:

generating by the PMIC a first alarm signal when the power supply voltage is higher than a reference voltage indicating a minimal normal-level power supply voltage for the mobile device, and generating a second alarm signal when the power supply voltage is lower than the reference voltage;

providing one of the first alarm signal and the second alarm signal from the PMIC to the SoC; and

determining the operating clock based on the provided one of the first alarm signal and the second alarm signal,

wherein the operating clock has a first frequency in response to the first alarm signal and a second frequency lower than the first frequency in response to the second alarm signal, and wherein the SoC further includes an interrupt controller,

the method further comprising generating by the interrupt controller an interrupt signal that controls the CPU responsive to the provided one of the first alarm signal and the second alarm signal.

2. The power management method of claim 1, further comprising:

generating in the SoC the operating clock by dividing a source clock received by the SoC using a clock division ratio selected in response to the one of the first alarm signal and the second alarm signal.

3. The power management method of claim 1, wherein the providing of the one of the first alarm signal and the second alarm signal to the SoC comprises:

comparing the power supply voltage to the reference voltage to generate the one of the first alarm signal and the second alarm signal.

4. A mobile device comprising:

a power management integrated circuit (PMIC) that receives a power supply voltage from a battery and compares the power supply voltage to a reference voltage indicating a minimal normal-level power supply voltage for the mobile device, wherein the PMIC generates a first alarm signal when the power supply voltage is higher than the reference voltage and generates a second alarm signal when the power supply voltage is lower than the reference voltage; and

a System-on-Chip (SoC) separate from the PMIC that receives one of the first alarm signal and the second alarm signal,

the SoC comprising

a Central Processing Unit (CPU) that operates in response to an operating clock,

a clock divider that generates the operating clock, wherein the operating clock is generated as having a first frequency in response to the first alarm signal and as having a second frequency lower than the first frequency in response to the second alarm signal, and

an interrupt controller that generates an interrupt signal that controls the CPU responsive to the one of the first alarm signal and the second alarm signal.

5. The mobile device of claim 4, wherein the clock divider generates the operating clock by dividing a source clock received by the SoC using a clock division ratio.

6. The mobile device of claim 5, wherein the clock division ratio comprises a first clock division ratio and a second clock division ratio different from the first clock division ratio, and

the clock divider generates the operating clock by either dividing the source clock using the first clock division ratio in response to the first alarm signal, or dividing the source clock using the second clock division ratio in response to the second alarm signal.

7. The mobile device of claim 6, wherein the SoC comprises a register storing clock division information defining the first clock division ratio and the second clock division ratio.

8. The mobile device of claim 4, wherein the PMIC comprises:

a reference voltage generator that generates the reference voltage; and

a comparator that compares the power supply voltage and the reference voltage to generate at least one of the first alarm signal and the second alarm signal.

9. The mobile device of claim 8, wherein the PMIC further comprises:

a register storing power management information, wherein the reference voltage generator generates the reference voltage in response to the power management information.

10. A mobile device, comprising:

a battery providing a power supply voltage;

a power management integrated circuit (PMIC) that compares the power supply voltage with a reference voltage indicating a minimal normal-level power supply voltage for the mobile device to provide a comparison signal, and generates an alarm signal from the comparison signal; and

a System-on-Chip (SoC) including a Central Processing Unit (CPU) that operates in response to an operating clock, a clock divider that generates the operating clock in response to the alarm signal, and a current control unit that generates clock division information and power management information,

wherein the PMIC comprises

a comparator that compares the power supply voltage and the reference voltage to generate the comparison signal in response to the power management information, and

a debounce circuit that receives the comparison signal and generates the alarm signal by removing a bounced signal portion of the comparison signal in response to the power management information,

wherein the power management information is communicated from the SoC to the PMIC via an interface connection, and the PMIC adjusts the reference voltage in response to the power management information.

11. The mobile device of claim 10, wherein the PMIC further comprises:

a register that stores the power management information received from the SoC via the interface connection; and

a reference voltage generator that generates the reference voltage in response to a first part of the stored power management information.

12. The mobile device of claim 11, wherein the PMIC further comprises:

a multiplexer that controls generation of the reference voltage in cooperation with the voltage reference generator, wherein the multiplexer selects one of a plurality of reference voltages as the reference voltage in response to the first part of the stored power management information.

13. The mobile device of claim 11, wherein the debounce circuit comprises:

a counter that decides a debounce time in response to another part of the stored power management information and counts the comparison signal according to the decided debounce time to provide a counter output;

an AND gate that performs an AND operation on the counter output and an internal clock to generate a flip-flop control signal; and

a flip-flop gated by the comparison signal and enabled by the flip-flop control signal to generate the alarm signal.

14. The mobile device of claim 13, wherein the PMIC further comprises:

an open drain pad that receives the alarm signal from the debounce circuit and provides the alarm signal to the SoC.

15. The mobile device of claim 10, wherein the SoC receives the alarm signal via a single general purpose input/output (I/O) pad.

16. The mobile device of claim 10, wherein the clock divider generates the operating clock as having a first frequency before the alarm signal is received by the SoC, and generates the operating clock as having a second frequency different from the first frequency after the alarm signal is received by the SoC.

17. The mobile device of claim 10, wherein the SoC further comprises a Graphics Processing Unit (GPU) that operates in response to the operating clock.