Ladar pulse deconfliction apparatus

• US 10,386,467 B2
• Filed: 02/14/2018
• Issued: 08/20/2019
• Est. Priority Date: 02/17/2017
• Status: Active Grant

• Current Assignee: AEye, Inc.
• Original Assignee: AEye, Inc.
• Inventors: Dussan, Luis Carlos, Steinhardt, Allan
• Primary Examiner(s): Hellner, Mark
• Application Number:
  US15/896,233
• Publication Number:
  US 20180238998A1
• Time in Patent Office: 552 Days
• Field of Search: 356 501
• CPC Class Codes: G01S 17/06 Systems determining position data of a target
• CPC Class Codes: G01S 17/10 using transmission of interrupted, pulse-modulated waves determination of distance by phase measurements G01S17/32
• CPC Class Codes: G01S 17/66 Tracking systems using electromagnetic waves other than radio waves
• CPC Class Codes: G01S 17/86 Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
• CPC Class Codes: G01S 17/931 of land vehicles
• CPC Class Codes: G01S 2013/9316 combined with communication equipment with other vehicles or with base stations
• CPC Class Codes: G01S 7/006 using shared front-end circuitry, e.g. antennas G01S13/765, G01S13/825 take precedence
• CPC Class Codes: G01S 7/4816 of receivers alone
• CPC Class Codes: G01S 7/484 Transmitters
• CPC Class Codes: G01S 7/4861 Circuits for detection, sampling, integration or read-out
• CPC Class Codes: G01S 7/4865 Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak peak detection in noise, signal conditioning G01S7/487
• CPC Class Codes: G01S 7/487 Extracting wanted echo signals , e.g. pulse detection
• CPC Class Codes: G01S 7/4873 by deriving and controlling a threshold value
• CPC Class Codes: G01S 7/4876 by removing unwanted signals G01S7/495 takes precedence

Abstract

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel filter is used at the receiver. Also, disclosed are techniques for selecting codes to use for the controllable delays as well as techniques for identifying and tracking interfering ladar pulses and their corresponding delay codes. The use of a ladar system with pulse deconfliction is also disclosed as part of an optical data communication system.

Claims

1. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a sparse delay sum circuit configured to detect own pulse reflections from doublet pulses having a known delay between pulses;

wherein the sparse delay sum circuit comprises;

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold;

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison; and

a register configured to store the controllable threshold; and

wherein the comparator is configured to read the controllable threshold from the register.

2. The apparatus of claim 1 wherein the sparse delay sum circuit further comprises:

compute logic configured controllably adjust the controllable threshold in the register based on a statistical analysis of the received signal.

22. The apparatus of claim 1 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

23. The apparatus of claim 1 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

3. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a sparse delay sum circuit configured to detect own pulse reflections from doublet pulses having a known delay between pulses;

wherein the sparse delay sum circuit comprises;

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold; and

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison; and

wherein the pulse deconfliction circuit is further configured to controllably adjust the known delay used by the delay circuit.

4. The apparatus of claim 3 wherein the pulse deconfliction circuit is further configured to controllably adjust the known delay used by the delay circuit based on a determined location for the ladar receiver.

5. The apparatus of claim 4 wherein the determined location comprises a cellular region.

25. The apparatus of claim 3 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

26. The apparatus of claim 3 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

6. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a sparse delay sum circuit configured to detect own pulse reflections from doublet pulses having a known delay between pulses;

wherein the sparse delay sum circuit comprises;

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold; and

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison; and

wherein the pulse deconfliction circuit is further configured to select the known delay used by the delay circuit based on hashing.

27. The apparatus of claim 6 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

28. The apparatus of claim 6 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

7. An apparatus 1 comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a sparse delay sum circuit configured to detect own pulse reflections from doublet pulses having a known delay between pulses;

wherein the sparse delay sum circuit comprises;

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold; and

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison; and

wherein the pulse deconfliction circuit is further configured to select the known delay used by the delay circuit based on a collaboration with a plurality of other ladar systems.

29. The apparatus of claim 7 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

30. The apparatus of claim 7 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

8. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a sparse delay sum circuit configured to detect own pulse reflections from doublet pulses having a known delay between pulses;

wherein the sparse delay sum circuit comprises;

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold; and

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison; and

wherein the pulse deconfliction circuit is further configured to select the known delay used by the delay circuit based on a posting by an electronic billboard.

31. The apparatus of claim 8 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

32. The apparatus of claim 8 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

9. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a cascaded sparse delay sum circuit that is configured to detect own pulse reflections from triplet pulses having known delays between pulses;

wherein the cascaded sparse delay sum circuit comprises;

a first delay circuit and a second delay circuit in series, the first delay circuit configured to delay a received signal by a first delay to generate a first delayed signal, the second delay circuit configured to delay the first delayed signal by a second delay to generate a second delayed signal, wherein the first and second delays correspond to the known delays;

a first adder configured to tap into the first delayed signal and sum the received signal with the first delayed signal to generate a first delay sum signal;

a second adder configured to tap into the second delayed signal and sum the first delay sum signal with the second delayed signal to generate a second delay sum signal;

a comparator configured to compare the second delay sum signal with a controllable threshold; and

logic configured to determine whether the second delay sum signal includes an own pulse reflection based on the threshold comparison.

10. The apparatus of claim 9 wherein the first and second delays are different delays.

11. The apparatus of claim 9 wherein the first and second delays are the same delay.

12. The apparatus of claim 9 wherein the sparse delay sum circuit further comprises:

a register configured to store the controllable threshold; and

wherein the comparator is configured to read the controllable threshold from the register.

13. The apparatus of claim 12 wherein the sparse delay sum circuit further comprises:

compute logic configured controllably adjust the controllable threshold in the register based on a statistical analysis of the received signal.

14. The apparatus of claim 9 wherein the pulse deconfliction circuit is further configured to controllably adjust the first and second delays used by the first and second delay circuits.

33. The apparatus of claim 9 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

34. The apparatus of claim 9 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

15. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the pulse deconfliction circuit comprises a cascaded sparse delay sum circuit that is configured to detect own pulse reflections from n-tuple pulses having known delays between pulses, wherein n is greater than 2;

wherein the cascaded sparse delay circuit comprises;

a plurality n of delay circuits in series, each delay circuit configured to delay a received signal by a different one of the known delays to generate a corresponding delayed signal;

a plurality n of adders in series, wherein a first adder in the series is configured to tap into a first corresponding delayed signal in the series and sum the received signal with the first corresponding delayed signal to generate a first delay sum signal, and wherein the subsequent adders in the series are configured to tap into corresponding delayed signals in the series and sum the corresponding delayed signal with the sum produced by the previous adder in the series;

a comparator configured to compare the sum from the n-th adder in the series with a controllable threshold; and

logic configured to determine whether the sum from the n-th adder in the series includes an own pulse reflection based on the threshold comparison.

16. The apparatus of claim 15 wherein the known delays between pulses comprise a plurality of different delays between at least a plurality of the pulses.

17. The apparatus of claim 15 wherein the known delays between pulses are the same delay between pulses.

35. The apparatus of claim 15 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

36. The apparatus of claim 15 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

18. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference; and

wherein the pulse deconfliction circuit comprises a triple comparator circuit, the triple comparator circuit configured to find an own pulse reflection in a received signal in response to (1) a sum of candidate pulse pairs having a magnitude in excess of a first threshold based on a first comparison operation, and (2) an inter-pulse deviation between candidate pulse pairs having a deviation less than a second threshold based on second and third comparison operations.

19. The apparatus of claim 18 wherein the triple comparator circuit comprises a sparse delay sum circuit configured to perform the first comparison operation.

20. The apparatus of claim 19 wherein the triple comparator circuit further comprises:

a first multiplier configured to multiply the received signal with the second threshold to generate a first product;

a first comparator configured to compare a delayed version of the received signal with the first product;

a second multiplier configured to multiply the delayed version of the received signal with the second threshold to generate a second product;

a first comparator configured to compare the received signal with the second product;

logic configured to detect the own pulse reflection based on results from the sparse delay sum circuit, the first comparator, and the second comparator.

21. The apparatus of claim 18 wherein the pulse deconfliction circuit is further configured to controllably adjust the second threshold based on the received signal and a delayed version of the received signal.

37. The apparatus of claim 18 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

38. The apparatus of claim 18 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

24. An apparatus comprising:

a ladar receiver that includes a pulse deconfliction circuit, wherein the pulse deconfliction circuit uses delays between pulses to distinguish between own pulse reflections and interference;

wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays; and

wherein the pulse deconfliction circuit is further configured to process incoming pulse reflections such that a first set of incoming pulse reflections are processed through a delay path and a second set of incoming pulse reflections are processed through a non-delayed path.

39. The apparatus of claim 24 wherein the ladar receiver includes a field programmable gate array (FPGA) on which the pulse deconfliction circuit is deployed.

40. The apparatus of claim 24 wherein the ladar receiver receives own pulse reflections that are spaced in a sequence of shorter delays between pulse pairs and longer delays between the pulse pairs with the shorter delays.

41. The apparatus of claim 24 wherein the pulse deconfliction circuit comprises a sparse delay sum circuit.

42. The apparatus of claim 24 wherein the sparse delay sum circuit is configured to detect own pulse reflections from doublet pulses having a known delay between pulses.

43. The apparatus of claim 42 wherein the sparse delay sum circuit comprises:

a delay circuit configured to delay a received signal by the known delay to generate a delayed signal;

an adder configured to sum the received signal with the delayed signal to generate a delay sum signal;

a comparator configured to compare the delay sum signal with a controllable threshold; and

logic configured to determine whether the delay sum signal includes an own pulse reflection based on the threshold comparison.

44. The apparatus of claim 24 wherein the sparse delay sum circuit comprises a cascaded sparse delay sum circuit that is configured to detect own pulse reflections from triplet pulses having known delays between pulses.

45. The apparatus of claim 24 wherein the sparse delay sum circuit comprises a cascaded sparse delay sum circuit that is configured to detect own pulse reflections from n-tuple pulses having known delays between pulses, wherein n is greater than 2.

46. The apparatus of claim 45 wherein the known delays between pulses comprise a plurality of different delays between at least a plurality of the pulses.

47. The apparatus of claim 45 wherein the known delays between pulses are the same delay between pulses.