Control circuit

• US 10,386,882 B2
• Filed: 04/14/2017
• Issued: 08/20/2019
• Est. Priority Date: 04/14/2017
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Kesarwani, Kapil
• Primary Examiner(s): Berhane, Adolf D
• Assistant Examiner(s): Ahmad, Shahzeb K
• Application Number:
  US15/487,746
• Publication Number:
  US 20180299919A1
• Time in Patent Office: 858 Days
• CPC Class Codes: G05F 3/26 Current mirrors
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A control circuit for generating a feedforward control signal based on an input voltage includes a divider coupled to the input voltage to generate a divided voltage and a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer. The control circuit also includes a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage and a current mirror circuit including a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated. A digitizing circuit is responsive to the current mirror output voltage to generate the feedforward control signal. A DC-DC converter and a method for generating a feedforward control signal based on an input voltage are also provided.

Claims

1. A control circuit for generating a feedforward control signal based on an input voltage, comprising:

a divider coupled to the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer;

a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to the first capacitor and to a reference current source and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated; and

a digitizing circuit responsive to the current mirror output voltage to generate the feedforward control signal, wherein the digitizing circuit comprises;

a first comparator responsive to the current mirror output voltage and to a first threshold signal to generate a first comparison signal indicative of a negative transient of the input voltage when the current mirror output voltage is greater than the first threshold signal; and

a second comparator responsive to the current mirror output voltage and to a second threshold signal to generate a second comparison signal indicative of a positive transient of the input voltage when the current mirror output voltage is less than the second threshold signal, wherein the feedforward control signal comprises configuration of the first comparison signal and the second comparison signal.

2. The control circuit of claim 1, further comprising a second capacitor coupled to the second current path of the current mirror, wherein the current mirror output voltage is generated across the second capacitor.

3. The control circuit of claim 2, wherein the first capacitor has a first capacitance value and the second capacitor has a second capacitance value that is different from the first capacitance value, and wherein the first and second capacitance values are selected such that the current mirror output voltage changes at a substantially same rate as the input voltage.

4. The control circuit of claim 1, wherein the first current path of the current mirror circuit comprises a first transistor having a first terminal coupled to the first capacitor, a second, control terminal, and a third terminal coupled to a reference potential, and wherein the second current path of the current mirror circuit comprises a second transistor having a first terminal coupled to the current mirror output node, a second, control terminal, and a third terminal coupled to the reference potential, wherein the control terminal of the first transistor is coupled to the control terminal of the second transistor.

5. The control circuit of claim 1, wherein the first threshold signal has a first voltage value and the second threshold signal has a second voltage value that is substantially different from the first voltage value.

6. The control circuit of claim 1, wherein the feedforward control signal is coupled to a digital compensator of a DC-DC converter.

7. The control circuit of claim 6, wherein the DC-DC converter is a buck regulator.

8. The control circuit of claim 1, further comprising a reset circuit configured to periodically reset the current mirror output voltage to a predetermined level.

9. The control circuit of claim 8, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage.

10. The control circuit of claim 9, further comprising a switch coupled between an output of the second buffer and the second capacitor and wherein the reset signal is coupled to a control terminal of the switch.

11. The control circuit of claim 10, wherein the switch is closed to reset the current mirror output voltage after a predetermined number of cycles of a system clock signal.

12. A DC-DC converter, comprising:

a power stage responsive to an input voltage and to a voltage control signal and configured to generate a regulated output voltage having a level that varies in response to the voltage control signal;

a control circuit for generating the voltage control signal, comprising;

a feedforward path, comprising;

a first divider coupled to the input voltage to generate a first divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the first divided voltage to generate a buffered voltage at an output of the first buffer;

a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to the first capacitor and to a reference current source and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated;

a digitizing circuit responsive to the current mirror output voltage to generate a feedforward control signal; and

a reset circuit configured to periodically reset the current mirror output voltage to a predetermined level, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage;

a feedback path, comprising;

a second divider coupled to the regulated output voltage to generate a second divided voltage having a value that is a fraction of the regulated output voltage;

an error amplifier responsive to the second divided voltage and to a reference voltage to generate an error voltage indicative of a difference between the second divided voltage and the reference voltage;

an ADC responsive to the error voltage to generate a feedback control signal;

a digital compensator responsive to the feedforward control signal and to the feedback control signal to generate a compensator signal; and

a pulse width modulator responsive to the compensator signal to generate the voltage control signal.

13. A method for generating a feedforward control signal based on an input voltage in a control circuit, comprising:

dividing the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

generating a buffered voltage at an output of a first buffer in response to the divided voltage;

generating a feedforward current through a first capacitor coupled to the first buffer output when there is a variation in the input voltage;

coupling a first current path of a current mirror circuit to the first capacitor and to a reference current source and coupling a second current path of the current mirror circuit to the reference current source;

generating a current mirror output voltage indicative of the input voltage variation at an output node of the current mirror circuit in the second current path, the current mirror output voltage being generated in response to the feedforward current and to a reference current received from the reference current source; and

generating the feedforward control signal in response to the current mirror output voltage; and

periodically resetting the current mirror output voltage to a predetermined level, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage.

14. A control circuit for generating a feedforward control signal based on an input voltage, comprising:

means for dividing the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer;

means for generating a feedforward current from the first buffer output when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to a reference current source and to the means for generating the feedforward current and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated; and

means for generating the feedforward control signal in response to the current mirror output voltage, wherein the means for generating the feedforward control signal comprises;

a first comparator responsive to the current mirror output voltage and to a first threshold signal to generate a first comparison signal indicative of a negative transient of the input voltage when the current mirror output voltage is greater than the first threshold signal; and

a second comparator responsive to the current mirror output voltage and to a second threshold signal to generate a second comparison signal indicative of a positive transient of the input voltage when the current mirror output voltage is less than the second threshold signal, wherein the feedforward control signal comprises configuration of the first comparison signal and the second comparison signal.

15. The control circuit of claim 14, wherein the first threshold signal has a first voltage value and the second threshold signal has a second voltage value that is substantially different from the first voltage value.

16. The control circuit of claim 14, wherein the feedforward control signal is coupled to a digital compensator of a DC-DC converter.

17. The control circuit of claim 14, further comprising a reset circuit configured to periodically reset the current mirror output voltage to a predetermined level.

18. The control circuit of claim 17, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage.

19. A control circuit for generating a feedforward control signal based on an input voltage, comprising:

a divider coupled to the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer;

a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to the first capacitor and to a reference current source and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated;

a digitizing circuit responsive to the current mirror output voltage to generate the feedforward control signal; and

a reset circuit configured to periodically reset the current mirror output voltage to a predetermined level, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage.

20. A DC-DC converter, comprising:

a power stage responsive to an input voltage and to a voltage control signal and configured to generate a regulated output voltage having a level that varies in response to the voltage control signal;

a control circuit for generating the voltage control signal, comprising;

a feedforward path, comprising;

a first divider coupled to the input voltage to generate a first divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the first divided voltage to generate a buffered voltage at an output of the first buffer;

a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to the first capacitor and to a reference current source and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated; and

a digitizing circuit responsive to the current mirror output voltage to generate a feedforward control signal, wherein the digitizing circuit comprises;

a first comparator responsive to the current mirror output voltage and to a first threshold signal to generate a first comparison signal indicative of a negative transient of the input voltage when the current mirror output voltage is greater than the first threshold signal; and

a second comparator responsive to current mirror output voltage and to a second threshold signal to generate a second comparison signal indicative of a positive transient of the input voltage when the current mirror output voltage is less than the second threshold signal, wherein the feedforward control signal comprises configuration of the first comparison signal and the second comparison signal;

a feedback path, comprising;

a second divider coupled to the regulated output voltage to generate a second divided voltage having a value that is a fraction of the regulated output voltage;

an error amplifier responsive to the second divided voltage and to a reference voltage to generate an error voltage indicative of a difference between the second divided voltage and the reference voltage;

an ADC responsive to the error voltage to generate a feedback control signal;

a digital compensator responsive to the feedforward control signal and to the feedback control signal to generate a compensator signal; and

a pulse width modulator responsive to the compensator signal to generate the voltage control signal.

21. A method for generating a feedforward control signal based on an input voltage in a control circuit, comprising:

dividing the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

generating a buffered voltage at an output of a first buffer in response to the divided voltage;

generating a feedforward current through a first capacitor coupled to the first buffer output when there is a variation in the input voltage;

coupling a first current path of a current mirror circuit to the first capacitor and to a reference current source and coupling a second current path of the current mirror circuit to the reference current source;

generating a current mirror output voltage indicative of the input voltage variation at an output node of the current mirror circuit in the second current path, the current mirror output voltage being generated in response to the feedforward current and to a reference current received from the reference current source;

generating the feedforward control signal in response to the current mirror output voltage;

generating a first comparison signal, by a first comparator of a digitizing circuit that is responsive to the current mirror circuit and to a first threshold signal, the first comparison signal indicative of a negative transient of the input voltage when the current mirror output voltage is greater than the first threshold signal; and

generating a second comparison signal, by a second comparator of a digitizing circuit that is responsive to the current mirror output voltage and to a second threshold signal, the second comparison signal indicative of a positive transient of the input voltage when the current mirror output voltage is less than the second threshold signal, wherein the feedforward control signal comprises configuration of the first comparison signal and the second comparison signal.

22. A control circuit for generating a feedforward control signal based on an input voltage, comprising:

means for dividing the input voltage to generate a divided voltage having a value that is a fraction of the input voltage;

a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer;

means for generating a feedforward current from the first buffer output when there is a variation in the input voltage;

a current mirror circuit comprising a first current path coupled to a reference current source and to the means for generating the feedforward current and a second current path coupled to the reference current source and comprising a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated;

means for generating the feedforward control signal in response to the current mirror output voltage; and

a reset circuit configured to periodically reset the current mirror output voltage to a predetermined level, wherein the reset circuit comprises a second buffer responsive to a third threshold signal to generate a reset signal to reset the current mirror output voltage.