Task processor
First Claim
1. A task execution system comprising:
- a processor including a first register and being configured to execute a task on the basis of data in the first register; and
a task control circuit including a second register and connected with the processor via a plurality of signal lines,wherein, when asserting a halt request signal to the processor via any of the signal lines, the task control circuit performs predetermined processing based on a parameter in the second register and then writes a return value indicating a result of the processing into the first register, and negates the halt request signal after completing the writing, andwherein the processor halts execution of a task when the halt request signal is asserted, and resumes execution of a task according to the return value written in the first register when the halt request signal is negated.
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Accused Products
Abstract
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
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Citations
15 Claims
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1. A task execution system comprising:
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a processor including a first register and being configured to execute a task on the basis of data in the first register; and a task control circuit including a second register and connected with the processor via a plurality of signal lines, wherein, when asserting a halt request signal to the processor via any of the signal lines, the task control circuit performs predetermined processing based on a parameter in the second register and then writes a return value indicating a result of the processing into the first register, and negates the halt request signal after completing the writing, and wherein the processor halts execution of a task when the halt request signal is asserted, and resumes execution of a task according to the return value written in the first register when the halt request signal is negated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A processor comprising:
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a processing register; and an execution control circuit configured to execute a task according to data in the processing register, wherein the execution control circuit halts execution of a task upon receiving a halt instruction from an external device and, when the halt instruction is canceled by the external device, resumes execution of a task according to data written into the processing register by the external device while the processing register is halted. - View Dependent Claims (12, 13, 14, 15)
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Specification