Apparatus and method for controlling a power supply to processing circuitry to avoid a potential temporary insufficiency in supply of power

• US 10,387,234 B2
• Filed: 08/05/2016
• Issued: 08/20/2019
• Est. Priority Date: 08/05/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Paterson, Richard, Harrison, Robert John, Uttley, Peter
• Primary Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US15/229,333
• Publication Number:
  US 20180039323A1
• Time in Patent Office: 1,110 Days
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A data processing apparatus 2 includes processing circuitry 4 performing processing operations which move the processing circuitry 4 between logical states. Monitoring circuitry 18 monitors logical state variables of the processing circuitry and these are supplied to prediction circuitry 30 which detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry 4. When such a pattern is detected, then power control circuitry 8,10 serves to trigger a mitigation response to counteract the future potential temporary insufficiency in power supply, such as temporarily reducing the clock frequency and/or boosting the supply voltage.

Claims

1. Apparatus for processing data comprising:

processing circuitry to perform data processing operations to move said processing circuitry between logical states specified by said data processing operations;

power supply circuitry to supply power to said processing circuitry;

monitoring circuitry to monitor one or more logical state variables of said processing circuitry indicative of a logical state of said processing circuitry;

fault detection circuitry to detect faults in operation of said processing circuitry;

voltage droop detecting circuitry to detect a droop having at least one predetermined characteristic in a voltage of a power supply signal supplied to said processing circuitry by said power supply circuitry;

pattern learning circuitry to identify a pattern in said one or more logical state variables that is correlated with detection of a fault by said fault detection circuitry and with detection of said droop;

prediction circuitry to consider the pattern identified by the pattern learning circuitry as a predetermined pattern, and to treat a subsequently detected occurrence of the predetermined pattern within said one or more logical state variables as being indicative of a future potential temporary insufficiency in supply of power by said power supply circuitry to said processing circuitry; and

power control circuitry responsive to detection of said predetermined pattern by said prediction circuitry to trigger a mitigation response to counteract said future potential temporary insufficiency.

2. Apparatus as claimed in claim 1, wherein said mitigation response comprises one or more of:

reducing a frequency of a clock signal supplied to said processing circuitry to regulate a rate of execution of said processing operations; and

increasing a voltage of a power supply signal supplied to said processing circuitry by said power supply circuitry.

3. Apparatus as claimed in claim 2, wherein said reducing said frequency comprises suppressing one or more clock cycles within said clock signal.

4. Apparatus as claimed in claim 3, wherein said reducing said frequency comprises suppressing a programmable number of clock cycles.

5. Apparatus as claimed in claim 4, wherein subsequent to suppressing said programmable number of clock cycles, said frequency is ramped back up to a nominal value by suppressing fewer subsequent clock cycles.

6. Apparatus as claimed in claim 2, said reducing said frequency comprises extending a time between a transition in a predetermined direction within said clock signal.

7. Apparatus as claimed in claim 1, wherein said processing circuitry comprises processing pipeline circuitry to perform a plurality of said processing operations in parallel and wherein said one or more logical state variables comprise one or more pipeline signals indicative of a logical state of said processing pipeline circuitry.

8. Apparatus as claimed in claim 7, wherein said processing pipeline circuitry executes program instructions and said one or more logical state variables include program instruction signals indicative of program instructions currently under execution by said processing pipeline circuitry.

9. Apparatus as claimed in claim 8, wherein said predetermined pattern includes one or more logical signals indicative of a wait-for-interrupt program instruction that pauses program execution until an interrupt signal is detected.

10. Apparatus as claimed in claim 1, wherein said fault detection circuitry comprises a watchdog timer circuit and a fault in operation of said processing circuitry is detected when said processing circuitry does not reset said watchdog timer circuit within a predetermined timer interval from a preceding reset of said watchdog timer circuit.

11. Apparatus as claimed in claim 1, wherein said predetermined pattern comprises a predetermined temporal sequence of logical state variables comprising a plurality of sampled logical states.

12. Apparatus as claimed in claim 11, wherein each of said plurality of sampled logical states comprises a plurality of logical sampled state variables.

13. Apparatus as claimed in claim 12, wherein monitoring circuitry comprises a ring buffer to store sample history data comprising a most recent sequence of sampled logical states.

14. Apparatus as claimed in claim 13, wherein said prediction circuitry detects said predetermined pattern within said most recent sequence of sampled logical states stored within said ring buffer.

15. Apparatus as claimed in claim 1, wherein said pattern learning circuitry comprises a programmable processor to execute program instructions to identify the pattern in said one or more logical state variables that is correlated with detection of a fault by said fault detection circuitry.

16. Apparatus for processing data comprising:

means for performing data processing operations to move said means for processing between logical states specified by said data processing operations;

means for supplying power to said means for processing;

means for monitoring one or more logical state variables of said means for processing indicative of a logical state of said means for processing;

means for detecting faults in operation of said means for processing;

means for detecting a droop having at least one predetermined characteristic in a voltage of a power supply signal supplied to said means for performing data processing by said means for supplying power;

means for identifying a pattern in said one or more logical state variables that is correlated with detection of a fault by said means for detecting and with detection of said droop;

means for considering the pattern identified by the means for identifying a pattern as a predetermined pattern and for treating a subsequently detected occurrence of the predetermined pattern within said one or more logical state variables as being indicative of a future potential temporary insufficiency in supply of power by said means for supplying power to said means for processing; and

means, responsive to detection of said predetermined pattern by said means for considering the pattern, for triggering a mitigation response to counteract said future potential temporary insufficiency.

17. A method of processing data comprising the steps of:

perform data processing operations with processing circuitry to move said processing circuitry between logical states specified by said data processing operations;

supplying power to said processing circuitry;

monitoring one or more logical state variables of said processing circuitry indicative of a logical state of said processing circuitry;

detecting a fault in operation of said processing circuitry;

detecting a droop having at least one predetermined characteristic in a voltage of a power supply signal supplied to said processing circuitry;

employing pattern learning circuitry to identify a pattern in said one or more logical state variables that is correlated with detection of the fault and with detection of said droop;

considering the pattern identified by the pattern learning circuitry as a predetermined pattern, and treating a subsequently detected occurrence of the predetermined pattern within said one or more logical state variables as being indicative of a future potential temporary insufficiency in supply of power to said processing circuitry; and

in response to detection of said predetermined pattern, triggering a mitigation response to counteract said future potential temporary insufficiency.