Non-volatile memory controller cache architecture with support for separation of data streams

• US 10,387,317 B2
• Filed: 08/22/2017
• Issued: 08/20/2019
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Camp, Charles J., Fisher, Timothy J., Fry, Aaron D., Ioannou, Nikolas, Koltsidas, Ioannis, Pletka, Roman, Tomic, Sasa, Walls, Andrew D.
• Primary Examiner(s): Tsui, Daniel D
• Application Number:
  US15/683,584
• Publication Number:
  US 20170351614A1
• Time in Patent Office: 728 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0884 Parallel mode, e.g. in parallel with main memory or CPU
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to: retrieve a physical block address corresponding to a logic block address; extract information from the physical block address; perform a lookup operation in cache using the extracted information; perform a range check of the physical block address in response to the lookup operation succeeding; and read data from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, in addition to supporting parallel writes to different non-volatile memory channels. The cache architecture also supports pipelining of the parallel writes to different non-volatile memory planes. The non-volatile memory controller is also configured to perform a direct memory lookup in the cache based on a physical block address.

Claims

1. A system, comprising:

non-volatile memory;

a non-volatile memory controller having a cache; and

logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to;

retrieve a physical block address corresponding to a logic block address;

extract information from the physical block address;

perform a lookup operation in cache using the extracted information;

perform a range check of the physical block address in response to the lookup operation succeeding; and

read data from the cache in response to the range check succeeding,

wherein an architecture of the cache supports separation of data streams,

wherein the cache architecture supports parallel writes to different non-volatile memory channels,

wherein the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes,

wherein the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.

2. The system of claim 1, comprising:

logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to;

receive a logical block address write request;

retrieve a previous physical block address and heat value associated with the logical block address from memory;

increment the heat value;

compute, by the non-volatile memory controller, a stream for the logic block address based on the incremented heat value;

increment a fill pointer of the stream;

write data of the logic block address write request to a page indexed by the incremented fill pointer; and

retrieve an updated physical block address of the page indexed by the incremented fill pointer,

wherein writing data to the page indexed by the incremented fill pointer is delayed when the fill pointer cannot be incremented.

3. The system of claim 2, comprising logic configured to:

update a logical to physical table with the updated physical block address; and

invalidate the previous physical block address.

4. The system of claim 1, wherein the extracted information includes a type of information selected from the group consisting of:

a stream, a plane, a channel and a block associated with the physical block address.

5. The system of claim 1, wherein the range check includes:

using a valid pointer and a fill pointer of the stream to determine whether the data is located in cache; and

determining a current write count of the cache,

wherein reading the data from the cache is delayed when the write count exceeds a threshold value.

6. The system of claim 1, wherein the non-volatile memory controller is configured to:

read the data from non-volatile memory in response to the range check failing; and

read the data from non-volatile memory in response to the lookup operation failing.

7. The system as recited in claim 1, wherein the non-volatile memory includes NAND Flash memory.

8. A computer-implemented method, comprising:

separating, using a non-volatile memory controller, data to be written to a non-volatile memory into multiple data streams in cache based on heat of the data; and

writing the separated data from the cache to the non-volatile memory in parallel through parallel writes to different channels and pipelining of those writes to different planes.

9. The computer-implemented method of claim 8, comprising:

performing a direct memory lookup in the cache based on a physical block address,

wherein performing the direct memory lookup in cache includes;

receiving a physical block address corresponding to a logic block address;

extracting information from the physical block address;

performing a lookup operation in cache using the extracted information;

performing a range check of the physical block address in response to the lookup operation succeeding;

reading data from cache in response to the range check succeeding; and

reading the data from non-volatile memory in response to the range check failing.

10. The computer-implemented method of claim 9, wherein the extracted information includes a type of information selected from the group consisting of:

a stream, a plane, a channel and a block associated with the physical block address.

11. The computer-implemented method of claim 9, wherein performing the range check includes:

using a valid pointer and a fill pointer of the stream to determine whether the data is located in cache; and

determining a current write count of the cache,

wherein reading the data from the cache is delayed when the write count exceeds a threshold value.

12. The computer-implemented method of claim 9, wherein the extracted information includes a type of information selected from the group consisting of:

a stream, a plane, a channel and a block associated with the physical block address wherein performing the direct memory lookup in cache includes;

read the data from non-volatile memory in response to the lookup operation failing.

13. The computer-implemented method of claim 8, comprising:

receiving a logic block address write request;

retrieving a previous physical block address and heat value associated with the logical block address from memory;

incrementing the heat value;

computing, by the non-volatile memory controller, a stream for the logic block address based on the incremented heat value;

incrementing a fill pointer of the stream;

writing data of the logic block address write request to a page indexed by the incremented fill pointer; and

retrieving an updated physical block address of the page indexed by the incremented fill pointer.

14. The computer-implemented method of claim 13, comprising:

updating a logical to physical table with the updated physical block address; and

invalidating the previous physical block address.

15. The computer-implemented method of claim 13, wherein writing data to the page indexed by the incremented fill pointer is delayed when the fill pointer cannot be incremented.

16. The computer-implemented method of claim 8, wherein the non-volatile memory includes NAND Flash memory.

17. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions readable and/or executable by a controller to cause the controller to:

separate, by the controller, data to be written to a non-volatile memory into multiple data streams based on heat of the data; and

write, by the controller, the separated data from a cache to the non-volatile memory in parallel through parallel writes to different channels and pipelining of those writes to different planes.

18. The computer program product of claim 17, the program instructions readable and/or executable by the controller to cause the controller to:

perform, by the controller, a direct memory lookup in the cache based on a physical block address,

wherein performing the direct memory lookup in cache includes;

receiving a physical block address corresponding to a logic block address;

extracting information from the physical block address;

performing a lookup operation in cache using the extracted information;

performing a range check of the physical block address in response to the lookup operation succeeding; and

reading data from cache in response to the range check succeeding.

19. The computer program product of claim 17, wherein the separating the data to be written to a non-volatile memory into multiple data streams in cache includes:

receiving a logic block address write request;

retrieving a previous physical block address and heat value associated with the logical block address from memory;

incrementing the heat value;

computing, by the controller, a stream for the logic block address based on the incremented heat value;

incrementing a fill pointer of the stream;

writing data of the logic block address write request to a page indexed by the incremented fill pointer; and

retrieving an updated physical block address of the page indexed by the incremented fill pointer.