Methods to store dynamic layer content inside a design file

• US 10,387,601 B2
• Filed: 11/22/2016
• Issued: 08/20/2019
• Est. Priority Date: 11/26/2015
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Jayaraman, Thirupurasundari, Kandukuri, Srikanth, Rouse, Gordon, Raman, Anil, Wu, Kenong, Gunasekaran, Praveen, Balaji, Aravindh, Jain, Ankit
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US15/358,888
• Publication Number:
  US 20170154147A1
• Time in Patent Office: 1,001 Days
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods are disclosed for storing dynamic layer content in a design file. A design file is received having design data corresponding to a plurality of process layers. A geometric operation formula is also received. A processor generates a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers. The updated design file is stored, the design file now having a polygon having dynamic layer content.

Claims

1. A method for storing dynamic layer content in a design file for a chip comprising:

receiving, at a processor, a design file having design data corresponding to a plurality of process layers;

receiving, at the processor, a geometric operation formula;

reading, using the processor, a plurality of cell indexes in the design file, each cell index having cell bounds and data corresponding to cell data of the chip;

retrieving, using the processor, the cell bounds associated with a cell index;

determining, using the processor, whether the cell bounds intersect with a region of interest;

determining, using the processor, whether the cell bounds contain a layer of interest;

retrieving, using the processor, the cell data if the cell bounds intersect with a region of interest and contain a layer of interest;

generating, using the processor, a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell data;

storing in the design file, using the processor, the polygon having dynamic layer content; and

inspecting a wafer with an inspection tool using the design file including the polygon having dynamic layer content.

2. The method of claim 1, wherein the geometric operation formula is associated with a specific chip area.

3. The method of claim 1, wherein the geometric operation formula is an OR operation.

4. The method of claim 1, wherein the geometric operation formula is an AND operation.

5. The method of claim 1, wherein the geometric operation formula is a GROW operation.

6. The method of claim 1, wherein the geometric operation formula is a SHRINK operation.

7. The method of claim 1, further comprising:

detecting, using the processor, one or more architecture-specific outlines in the design file, wherein the polygon is formed by applying the geometric operation formula on the one or more architecture-specific outlines.

8. A system for storing dynamic layer content in a design file comprising:

a design file storage device configured to store one or more design files, each design file having design data corresponding to a plurality of process layers for a chip, wherein each design file has a plurality of cell indexes, each cell index having cell bounds and cell design data;

a geometric operation formula database configured to store one or more geometric operation formulas;

a processor in electronic communication with the design file storage device and the geometric operation formula database, the processor configured to;

receive, from the design file storage device, a design file for a specific chip;

receive, from the geometric operation formula database, a geometric operation formula;

retrieve the cell bounds associated with a cell index;

determine whether the cell bounds intersect with a region of interest;

determine whether the cell bounds contain a layer of interest;

retrieve the cell design data if the cell bounds intersect with a region of interest and contain a layer of interest;

generate a polygon having dynamic layer content by applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell design data of the design file;

update the design file to include the polygon having dynamic layer content; and

an inspection tool in electronic communication with the design file storage device, the inspection tool configured to inspect a wafer using the design file including the polygon having dynamic layer content.

9. The system of claim 8, wherein the geometric operation formula is associated with a specific chip structure.

10. The system of claim 8, wherein the geometric operation formula is an OR operation.

11. The system of claim 8, wherein the geometric operation formula is an AND operation.

12. The system of claim 8, wherein the geometric operation formula is a GROW operation.

13. The system of claim 8, wherein the geometric operation formula is a SHRINK operation.

14. The system of claim 8, wherein the processor is further configured to:

detect one or more architecture-specific outlines in the design file,

wherein the polygon is generated by applying the geometric operation formula on the one or more architecture-specific outlines.

15. The system of claim 8, wherein the geometric operation formula corresponds to the specific chip.

16. The system of claim 8, wherein the geometric operation formula corresponds to one or more process layers on the chip.

17. A non-transient computer readable medium containing program instructions for causing a computer to perform the method of:

receiving, at the computer, a design file having design data corresponding to a plurality of process layers;

receiving, at the computer, a geometric operation formula;

reading, using the computer, a plurality of cell indexes in the design file, each cell index having cell bounds and data corresponding to cell data of the chip;

retrieving, using the computer, the cell bounds associated with a cell index;

determining, using the computer, whether the cell bounds intersect with a region of interest;

determining, using the computer, whether the cell bounds contain a layer of interest;

retrieving, using the computer, the cell data if the cell bounds intersect with a region of interest and contain a layer of interest;

generating, using the computer, a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell data;

storing in the design file, using the computer, the polygon having dynamic layer content; and

instructing, using the computer, an inspection tool to inspect a wafer using the design file including the polygon having dynamic layer content.