Active matrix substrate and display device

• US 10,388,238 B2
• Filed: 08/09/2018
• Issued: 08/20/2019
• Est. Priority Date: 01/21/2013
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Fujikawa, Yohsuke
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): Zubajlo, Jennifer L
• Application Number:
  US16/059,080
• Publication Number:
  US 20180350314A1
• Time in Patent Office: 376 Days
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.

Claims

1. An active matrix substrate comprising:

a plurality of data lines and a plurality of scanning lines that are arranged in a matrix;

a plurality of switching elements that are provided each at one of a corresponding crossing of the plurality of data lines with the plurality of scanning lines;

a plurality of pixels that include pixel electrodes connected to the plurality of switching elements;

a plurality of terminals are provided to input external signals to the plurality of data lines or the plurality of scanning lines; and

a plurality of signal lines are defined in a line region between a matrix region in which the plurality of data lines and the plurality of scanning lines are arranged in the matrix and a terminal region in which the plurality of terminals are arranged, and the line region is defined so that a line pitch becomes narrower in a direction from the matrix region to the terminal region, wherein

one end of each of the plurality of signal lines is connected to drive one of the plurality of data lines or one of the plurality of scanning lines, and another end of each of the plurality of signal lines is connected to one of the plurality of terminals,

each of the plurality of signal lines includes a first line portion provided on a matrix region side, a second line portion provided on a terminal region side, and a connection portion that connects the first line portion and the second line portion,

the first line portion and the second line portion of one of two adjacent signal lines of the plurality of signal lines are made of a first conductive layer and a second conductive layer, respectively, which are different from each other, and the first line portion and the second line portion of the other of the two adjacent signal lines are made of the second conductive layer and the first conductive layer, respectively,

a position of the connection portion of each of the plurality of signal lines is determined in accordance with a layout position of the respective signal line in the line region,

the plurality of signal lines include a second line group in which positioning to connect the signal lines to the terminals is made by bending the second line portions and a first line group in which positioning to connect the signal lines to the terminals is made by bending the first line portions, and

an arrangement interval of the connection portions of the plurality of signal lines in the second line group is larger than an arrangement interval of the connection portions of the plurality of signal lines in the first line group.

2. The active matrix substrate according to claim 1, wherein

a driver IC is connected to the plurality of terminals, and

bending points of the second line portions are spaced away from the driver IC, and an empty space is defined between the driver IC and the line group in which positioning to connect the signal lines to the terminals is made by bending the second line portions.

3. The active matrix substrate according to claim 2, wherein another electrode is arranged in the empty space.

4. The active matrix substrate according to claim 1, wherein an interconnection length in the second line group is longer than an interconnection length in the first line group.

5. The active matrix substrate according to claim 1, wherein the second line portions of the first line group are not bent.