Semiconductor device and memory circuit having an OS transistor and a capacitor
First Claim
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1. A semiconductor device comprising:
- a first transistor including an oxide semiconductor in a channel formation region;
second to fourth transistors;
a capacitor; and
first to fifth wirings,wherein;
the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor and one of electrodes of the capacitor,a gate of the first transistor is electrically connected to the second wiring,the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor,a gate of the second transistor is electrically connected to the third wiring,the other of the source and the drain of the third transistor is electrically connected to the other of electrodes of the capacitor and the fourth wiring, anda gate of the fourth transistor is electrically connected to the fifth wiring;
wherein the second wiring is configured to provide a first voltage and the third wiring is configured to provide a second voltage different from the first voltage.
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Abstract
Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
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Citations
14 Claims
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1. A semiconductor device comprising:
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a first transistor including an oxide semiconductor in a channel formation region; second to fourth transistors; a capacitor; and first to fifth wirings, wherein; the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor and one of electrodes of the capacitor, a gate of the first transistor is electrically connected to the second wiring, the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, a gate of the second transistor is electrically connected to the third wiring, the other of the source and the drain of the third transistor is electrically connected to the other of electrodes of the capacitor and the fourth wiring, and a gate of the fourth transistor is electrically connected to the fifth wiring; wherein the second wiring is configured to provide a first voltage and the third wiring is configured to provide a second voltage different from the first voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first memory circuit; a second memory circuit, the second memory circuit comprising; a first transistor including an oxide semiconductor in a channel formation region; second to fourth transistors; and a capacitor, and first to fifth wirings, wherein; the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor and one of electrodes of the capacitor, a gate of the first transistor is electrically connected to the second wiring, the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, a gate of the second transistor is electrically connected to the third wiring, the other of the source and the drain of the third transistor is electrically connected to the other of electrodes of the capacitor and the fourth wiring, a gate of the fourth transistor is electrically connected to the fifth wiring, the first memory circuit is configured to store data acquired from an outside, and the second memory circuit is configured to store reference data; wherein the second wiring is configured to provide a first voltage and the third wiring is configured to provide a second voltage different from the first voltage. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsTamura, Hikaru
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Primary Examiner(s)Cho, Sung Il
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Application NumberUS15/823,662Publication NumberTime in Patent Office630 DaysField of Search36518505US Class CurrentCPC Class CodesG11C 11/40 using transistorsG11C 16/10 Programming or data input c...G11C 7/1078 Data input circuits, e.g. w...G11C 7/16 Storage of analogue signals...
