Semiconductor device and manufacturing method thereof

• US 10,388,538 B2
• Filed: 10/24/2016
• Issued: 08/20/2019
• Est. Priority Date: 03/05/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kishida, Hideyuki
• Primary Examiner(s): Harrison, Monica D
• Assistant Examiner(s): Lin, John
• Application Number:
  US15/332,198
• Publication Number:
  US 20170040181A1
• Time in Patent Office: 1,030 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/137 characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/3228 of AIIIBV compounds, e.g. to make them semi-insulating
• CPC Class Codes: H01L 21/477 : Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 : with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/247 : Amorphous materials
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Claims

1. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer overlapping with the gate electrode and in contact with the gate insulating layer, the oxide semiconductor layer comprising indium;

adding a halogen element into the oxide semiconductor layer after the formation of the oxide semiconductor layer;

performing first heat treatment on the oxide semiconductor layer after the addition of the halogen element;

adding oxygen into the oxide semiconductor layer by ion doping or ion implantation after the first heat treatment;

forming a source electrode and a drain electrode each having an end portion overlapping with the gate electrode and in contact with the oxide semiconductor layer after the addition of oxygen into the oxide semiconductor layer; and

forming an insulating layer overlapping with a channel formation region of the oxide semiconductor layer and in contact with the oxide semiconductor layer.

2. The manufacturing method of a semiconductor device according to claim 1, wherein second heat treatment is performed after the addition of oxygen into the oxide semiconductor layer.

3. The manufacturing method of a semiconductor device according to claim 1, wherein the first heat treatment is performed at a temperature higher than or equal to 250°

C. and lower than or equal to 600°

C.

4. The manufacturing method of a semiconductor device according to claim 1, wherein third heat treatment is performed after the step of forming the oxide semiconductor layer.

5. The manufacturing method of a semiconductor device according to claim 1, wherein the halogen element is fluorine.

6. The manufacturing method of a semiconductor device according to claim 1, wherein the halogen element is added into the oxide semiconductor layer by one of plasma doping, ion doping, and ion implantation.

7. A manufacturing method of a semiconductor device, comprising a step of forming a second transistor using the manufacturing method of a semiconductor device according to claim 1, over an insulating film formed over a first transistor.

8. A manufacturing method of a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium;

adding a halogen element into the oxide semiconductor layer after the formation of the oxide semiconductor layer;

performing first heat treatment on the oxide semiconductor layer after the addition of the halogen element; and

adding oxygen into the oxide semiconductor layer by ion doping or ion implantation after the first heat treatment.

9. The manufacturing method of a semiconductor device according to claim 8, wherein the halogen element is fluorine.

10. The manufacturing method of a semiconductor device according to claim 8, wherein the halogen element is added into the oxide semiconductor layer by one of plasma doping, ion doping, and ion implantation.

11. A manufacturing method of a semiconductor device, comprising the steps of:

forming a source electrode and a drain electrode over a substrate having an insulating surface;

forming an oxide semiconductor layer covering an end portion of the source electrode and an end portion of the drain electrode, the oxide semiconductor layer comprising indium;

adding a halogen element into the oxide semiconductor layer after the formation of the oxide semiconductor layer;

performing first heat treatment on the oxide semiconductor layer after the addition of the halogen element;

adding oxygen into the oxide semiconductor layer by ion doping or ion implantation after the first heat treatment;

forming a gate insulating layer overlapping with the end portion of the source electrode and the end portion of the drain electrode and in contact with the oxide semiconductor layer after the addition of oxygen into the oxide semiconductor layer; and

forming a gate electrode overlapping with the end portion of the source electrode and the end portion of the drain electrode and in contact with the gate insulating layer.

12. The manufacturing method of a semiconductor device according to claim 11, wherein second heat treatment is performed after the addition of oxygen into the oxide semiconductor layer.

13. The manufacturing method of a semiconductor device according to claim 11, wherein the first heat treatment is performed at a temperature higher than or equal to 250°

C. and lower than or equal to 600°

C.

14. The manufacturing method of a semiconductor device according to claim 11, wherein third heat treatment is performed after the step of forming the oxide semiconductor layer.

15. The manufacturing method of a semiconductor device according to claim 11, wherein the halogen element is fluorine.

16. The manufacturing method of a semiconductor device according to claim 11, wherein the halogen element is added into the oxide semiconductor layer by one of plasma doping, ion doping, and ion implantation.

17. A manufacturing method of a semiconductor device, comprising a step of forming a second transistor using the manufacturing method of a semiconductor device according to claim 11, over an insulating film formed over a first transistor.