Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors

• US 10,388,572 B2
• Filed: 03/06/2017
• Issued: 08/20/2019
• Est. Priority Date: 03/06/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Liu, Xuefeng, Wu, Heng, Xu, Peng
• Primary Examiner(s): Inoussa, Mouloucoulaye
• Application Number:
  US15/450,193
• Publication Number:
  US 20180254218A1
• Time in Patent Office: 897 Days
• Field of Search: 257532, 257E21008, 257E29342, 438381
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a substrate comprising a lower source/drain layer disposed between a base semiconductor substrate and a layer of semiconductor material;

patterning the layer of semiconductor material to form at least a first vertical semiconductor fin and a second vertical semiconductor fin;

forming trench isolation regions through portions of the lower source/drain layer and into the semiconductor substrate to define a plurality of device regions comprising a first device region, a second device region, and a third device region, wherein the first device region comprises the first vertical semiconductor fin and a first lower source/drain region, and wherein the second device region comprises the second vertical semiconductor fin and a second lower source/drain region;

concurrently forming (i) a first gate structure surrounding sidewalls of the first vertical semiconductor fin in the first device region, and (ii) a first capacitor electrode in the third device region, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode;

wherein the first gate electrode and the first capacitor electrode are concurrently formed from a same first layer of conductive material by depositing and patterning said same first layer of conductive material; and

concurrently forming (i) a second gate structure surrounding sidewalls of the second vertical semiconductor fin in the second device region, (ii) a capacitor insulator layer on the first capacitor electrode and (iii) a second capacitor electrode on the capacitor insulator layer in the third device region, wherein the second gate structure comprises a second gate dielectric layer and a second gate electrode;

wherein the second gate dielectric layer and the capacitor insulator layer are concurrently formed from a same conformal layer of dielectric material by depositing and patterning said same conformal layer of dielectric material;

wherein the second gate electrode and the second capacitor electrode are concurrently formed from a same second layer of conductive material by depositing and patterning said same second layer of conductive material;

wherein concurrently forming the first gate structure in the first device region and the first capacitor electrode in the third device region, comprises;

depositing a first conformal layer of dielectric material within the first, second and third device regions;

depositing the first layer of conductive material over the first conformal layer of dielectric material within the first, second, and third device regions;

planarizing a surface of the semiconductor device to remove overburden portions of the first layer of conductive material and the first conformal layer of dielectric material disposed over upper surfaces of the first and second vertical semiconductor fins in the first and second device regions;

forming a first cut mask on the planarized surface of the semiconductor device, wherein the first cut mask comprises an image of the first gate structure and the first capacitor electrode; and

etching portions of the first layer of conductive material and the first conformal layer of dielectric material, which are exposed through the first cut mask, to concurrently form the first gate structure and the first capacitor electrode in the first and third device regions, while removing portions of the first conformal layer of gate dielectric material and the first layer of conductive material within the second device region,

wherein a remaining portion of the first conformal layer of dielectric material in the first device region forms the first gate dielectric layer of the first gate structure.

2. The method of claim 1, further comprising:

forming a lower insulating spacer on the first and second lower source/drain regions, wherein the lower insulating spacer electrically insulates the first and second lower source/drain regions from the first and second gate structures;

forming an upper insulating spacer on upper surfaces of the first and second gate structures, and on an upper surface of a capacitor structure formed by the first and second capacitor electrodes and the capacitor insulator layer in the third device region; and

forming a first upper source/drain region on an upper surface of the first vertical semiconductor fin, and a second upper source/drain region on an upper surface of the second vertical semiconductor fin.

3. The method of claim 1, wherein the layer of semiconductor material comprises a layer of monocrystalline semiconductor material.

4. The method of claim 1, wherein depositing the first conformal layer of dielectric material comprises depositing one or more conformal layers of high-k dielectric material, wherein k is about 3.9 or greater.

5. The method of claim 1, wherein concurrently forming the second gate structure, the capacitor insulator layer, and the second capacitor electrode, comprises:

depositing said same conformal layer of dielectric material within the first, second and third device regions;

depositing the second layer of conductive material over said same conformal layer of dielectric material within the first, second, and third device regions;

planarizing a surface of the semiconductor device to remove overburden portions of the second layer of conductive material and said same conformal layer of dielectric material disposed over upper surfaces of the first and second vertical semiconductor fins in the first and second device regions, and an upper surface of the first capacitor electrode in the third device region;

forming a second cut mask on the planarized surface of the semiconductor device, wherein the second cut mask comprises openings that are aligned with, or at least overlap portions of, respective trench regions of the plurality of trench regions; and

etching trenches in portions of the second layer of conductive material, which are exposed through the openings of the second cut mask, to concurrently form the second gate structure in the second device region, and the second capacitor electrode in the third device region; and

filling the trenches with insulating material.

6. The method of claim 5, wherein the first conformal layer of dielectric material and said same conformal layer of dielectric material are formed of different dielectric materials.

7. The method of claim 5, wherein a thickness of the first conformal layer of dielectric material is less than a thickness of said same conformal layer of dielectric material.

8. The method of claim 1, wherein the first capacitor electrode and the second capacitor electrode each comprise a plurality of parallel vertical conductive fins that are disposed in an overlapped, interdigitated configuration, with the capacitor insulator layer disposed between the first and second capacitor electrodes.