Semiconductor devices and fabrication methods thereof

• US 10,388,575 B2
• Filed: 05/21/2018
• Issued: 08/20/2019
• Est. Priority Date: 05/22/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/985,278
• Publication Number:
  US 20180337099A1
• Time in Patent Office: 456 Days
• Field of Search: 438169, 257330, 257351, 257371
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a semiconductor structure includes providing a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region; forming a first work function layer on the first region, the transition region, and the second region; removing a first portion of the first work function layer formed in the transition region; forming a hard mask layer on the base substrate in the transition region and on the first work function layer in the second region; removing a second portion the first work function layer formed in the first region using the hard mask layer as an etch mask; removing the hard mask layer; and forming a second work function layer, on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

Claims

1. A method for fabricating a semiconductor structure, comprising:

providing a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region;

forming a first work function layer on the first region, the transition region, and the second region of the base substrate;

removing a first portion of the first work function layer formed in the transition region;

forming a hard mask layer on the base substrate in the transition region and on the first work function layer in the second region;

removing a second portion the first work function layer formed in the first region using the hard mask layer as an etch mask;

removing the hard mask layer; and

forming a second work function layer, on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

2. The method according to claim 1, wherein removing the first portion of the first work function layer formed in the transition region includes:

forming a protection layer on the first work function layer;

forming a patterned layer on the protection layer to expose the first portion of the first work function layer formed in the transition region;

removing the protection layer formed in the transition region and the first portion of the first work function layer formed in the transition region using the patterned layer as an etch mask; and

removing the patterned layer and the protection layer.

3. The method according to claim 2, wherein:

the protection layer is made of at least one of polycrystalline silicon and amorphous silicon.

4. The method according to claim 2, wherein:

removing the protection layer formed in the transition region and the first portion of the first work function layer formed in the transition region includes a dry etching process.

5. The method according to claim 4, wherein process parameters used in the dry etching process include:

an etch gas including CF₄, SF₆, Cl₂, and O₂;

a flowrate of CF₄ in a range of approximately 10 sccm to 500 sccm;

a flowrate of SF₆ in a range of approximately 20 sccm to 300 sccm;

a flowrate of Cl₂ in a range of approximately 6 sccm to 120 sccm;

a flowrate of O₂ in a rage of approximately 1 sccm to 90 sccm;

a process pressure in a range of approximately 1 mTorr to 250 mTorr; and

a process power in a range of approximately 100 W to 500 W.

6. The method according to claim 2, wherein:

an ashing process is performed to remove the patterned layer.

7. The method according to claim 1, wherein:

a width of the transition region is in a range of approximately 36 nm to 86 nm.

8. The method according to claim 1, wherein:

a plurality of first devices are formed in the first region; and

a plurality of second devices are formed in the second region.

9. The method according to claim 8, wherein:

a type of the plurality of first devices formed in the first region is different from a type of the plurality of second devices formed in the second region.

10. The method according to claim 9, wherein:

the plurality of first devices are N-type metal-oxide-semiconductor (NMOS) devices; and

the plurality of second devices are P-type metal-oxide-semiconductor (PMOS) devices.

11. The method according to claim 10, wherein:

the first work function layer is made of at least one of TiN, TaN, and TiSiN.

12. The method according to claim 11, wherein:

a thickness of the first work function layer is in a range of approximately 25 Å and

50 Å

.

13. The method according to claim 10, wherein:

the second work function layer is made of at least one of TiAl, Al, TiC, and TiCAl.

14. The method according to claim 13, wherein:

a thickness of the second work function layer is in a range of approximately 30 Å and

60 Å

.

15. The method according to claim 1, prior to forming the first work function layer, further including:

forming a high-k dielectric layer on the base substrate.

16. The method according to claim 1, wherein:

the base substrate includes a substrate and a plurality of discrete fin structures formed on the substrate.