Wafer scale testing and initialization of small die chips

• US 10,388,578 B2
• Filed: 10/27/2017
• Issued: 08/20/2019
• Est. Priority Date: 10/02/2017
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Horibe, Akihiro, Kohda, Yasuteru, Munetoh, Seiji, Subramanian, Chitra, Sueoka, Kuniaki
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/795,888
• Publication Number:
  US 20190103328A1
• Time in Patent Office: 662 Days
• Field of Search: 257 48, 257620
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1434 Memory

Abstract

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Claims

1. A method for testing a chip area comprising:

fabricating a chip intermediate body including a semiconductor region, a cut region, a contact region, a test area, and electric wiring, the semiconductor region including a plurality of chip areas arranged as an array and respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the chip areas across the cut region with a contact pad corresponding to each row of chip areas in the array, the test area including a test circuit corresponding to each column of chip areas in the array, the electric wiring being provided continuously with the cut region to connect the chip areas and the contact region; and

testing the chip areas in parallel with a probe of a test unit contacting the contact region.

3. The method as recited in claim 1, wherein testing the chip areas in parallel includes writing initial data to the chip areas using test circuits provided opposite to the chip areas across the cut region to detect logic functionality.

4. The method as recited in claim 1, further including initializing each of the chip areas in a wafer-level initialization for chip areas that pass the testing.

5. The method as recited in claim 4, wherein the initialization includes loading each chip area with a key and initial-bootloader code.

6. The method as recited in claim 4, wherein the wafer-level initialization initializes every chip area in parallel.

2. A method for fabricating a semiconductor chip comprising:

testing a semiconductor region provided on a chip intermediate body with a probe of a test unit, the chip intermediate body including the semiconductor region, a cut region, a contact region, a test area, and electric wiring, the semiconductor region including a plurality of chip areas arranged as an array and respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the chip areas across the cut region with a contact pad corresponding to each row of chip areas in the array, the test area including a test circuit corresponding to each column of chip areas in the array, the electric wiring being provided continuously with the cut region to connect the chip areas and the contact region; and

cutting the cut region to cut out the semiconductor chips.

7. The method as recited in claim 2, wherein testing the chip areas in parallel includes writing initial data to the chip areas using test circuits provided opposite to the chip areas across the cut region to detect logic functionality.

8. The method as recited in claim 2, further including initializing each of the chip areas in a wafer-level initialization for chip areas that pass the testing.

9. The method as recited in claim 8, wherein the initialization includes loading each chip area with a key and initial-bootloader code.

10. The method as recited in claim 8, wherein the wafer-level initialization initializes every chip area in parallel.