Semiconductor device and method of forming flipchip interconnect structure

• US 10,388,626 B2
• Filed: 11/16/2010
• Issued: 08/20/2019
• Est. Priority Date: 03/10/2000
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Pendse, Rajendra D.
• Primary Examiner(s): Wilczewski, Mary A
• Assistant Examiner(s): Chiu, Tsz K
• Application Number:
  US12/947,414
• Publication Number:
  US 20110074022A1
• Time in Patent Office: 3,199 Days
• Field of Search: 257737, 257738, 257778, 257E21508, 257E21511, 257E23021
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/27013 : for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/29109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81345 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308

Abstract

A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die including a plurality of interconnect structures formed over a surface of the semiconductor die;

providing a substrate;

forming a plurality of conductive traces with interconnect sites disposed at intermediate locations along a length of the conductive traces over the substrate with the conductive traces extending in opposite directions from the interconnect sites;

forming a plurality of individual non-conductive masking patches over an area of the substrate interstitial between and physically separated from the interconnect sites, wherein the interconnect structures including a width substantially the same as a width of the conductive traces away from the interconnect sites and wider than the interconnect sites;

bonding the interconnect structures to the interconnect sites absent a mask opening so that the interconnect structures cover a top surface and side surfaces of the interconnect sites; and

depositing an encapsulant around the interconnect structures between the semiconductor die and substrate.

2. The method of claim 1, further including bonding the interconnect structures to the interconnect sites under pressure or reflow temperature.

3. The method of claim 1, further including forming a masking layer over an area of the substrate away from the interconnect sites.

4. The method of claim 1, wherein the interconnect structures include bumps or bump material.

5. The method of claim 1, wherein the interconnect structures include a fusible portion and non-fusible portion.

6. The method of claim 1, wherein the interconnect structures include a conductive pillar and bump formed over the conductive pillar.

7. The method of claim 1, further including forming asperities over the interconnect sites or interconnect structures.

8. A method of making a semiconductor device, comprising:

providing a semiconductor die including an interconnect structure formed over a surface of the semiconductor die;

providing a substrate;

forming a conductive trace with an interconnect site disposed at an intermediate location along the conductive trace over the substrate with the conductive trace extending in opposite directions from the interconnect site, the interconnect site being narrower than the interconnect structure;

forming a plurality of individual non-conductive masking patches over an area of the substrate interstitial around and physically separated from the interconnect site; and

bonding the interconnect structure to the interconnect site absent a mask opening so that the interconnect structure covers a top surface and side surfaces of the interconnect site.

9. The method of claim 8, further including bonding the interconnect structure to the interconnect site under pressure or reflow temperature.

10. The method of claim 8, further including depositing an encapsulant around the interconnect structure between the semiconductor die and substrate.

11. The method of claim 10, further including forming a masking layer over an area of the substrate away from the interconnect site.

12. The method of claim 11, wherein the masking layer forms a dam to block the encapsulant from extending beyond a footprint of the semiconductor die.

13. The method of claim 8, wherein the interconnect structure includes a fusible portion and non-fusible portion.

14. The method of claim 8, further including forming asperities over the interconnect site or interconnect structure.

15. A semiconductor device, comprising:

a semiconductor die including a plurality of interconnect structures formed over a surface of the semiconductor die;

a substrate;

a plurality of conductive traces with interconnect sites disposed at intermediate locations along a length of the conductive traces formed over the substrate with the conductive traces extending in opposite directions from the interconnect sites, the interconnect sites including a width substantially the same as a width of the conductive traces away from the interconnect sites and narrower than the interconnect structures to increase interconnect density;

a plurality of individual non-conductive masking patches formed over an area of the substrate interstitial between and physically separated from the interconnect sites, wherein the interconnect structures are bonded to the interconnect sites so that the interconnect structures cover a top surface and side surfaces of the interconnect sites; and

an encapsulant deposited around the interconnect structures between the semiconductor die and substrate.

16. The semiconductor device of claim 15, wherein the interconnect structures are bonded to the interconnect sites under pressure or reflow temperature.

17. The semiconductor device of claim 15, wherein the interconnect structures include a fusible portion and non-fusible portion.

18. The semiconductor device of claim 15, wherein the interconnect structures include a conductive pillar and bump formed over the conductive pillar.

19. The semiconductor device of claim 15, further including asperities formed over the interconnect sites or interconnect structures.

20. A semiconductor device, comprising:

a substrate;

a conductive trace with an interconnect site disposed at an intermediate location along the conductive trace formed over the substrate with the conductive trace extending in opposite directions from the interconnect site;

a plurality of individual non-conductive masking patches formed over an area of the substrate interstitial around and physically separated from the interconnect site;

a semiconductor die including an interconnect structure formed over a surface of the semiconductor die with the interconnect structure bonded to the interconnect site absent a mask opening so that the interconnect structure covers a top surface and side surfaces of the interconnect site; and

an encapsulant deposited around the interconnect structure between the semiconductor die and substrate.

21. The semiconductor device of claim 20, wherein the interconnect structure is bonded to the interconnect site under pressure or reflow temperature.

22. The semiconductor device of claim 20, wherein a masking layer is formed over an area of the substrate away from the interconnect site.

23. The semiconductor device of claim 20, wherein the interconnect structure includes a bump or bump material.

24. The semiconductor device of claim 20, wherein the interconnect structure includes a fusible portion and non-fusible portion.

25. The semiconductor device of claim 20, wherein the interconnect structure includes a conductive pillar and bump formed over the conductive pillar.

26. A semiconductor device, comprising:

a substrate;

a conductive trace with an interconnect site disposed at an intermediate location along a length of the conductive trace formed over the substrate;

a plurality of individual non-conductive masking patches formed over an area of the substrate interstitial around and physically separated from the interconnect site; and

a semiconductor die including an interconnect structure formed over a surface of the semiconductor die with the interconnect structure covering a top surface and side surfaces of the interconnect site.

27. The semiconductor device of claim 26, wherein the interconnect structure is bonded to the interconnect site under pressure or reflow temperature.

28. The semiconductor device of claim 26, wherein a masking layer is formed over an area of the substrate away from the interconnect site.

29. The semiconductor device of claim 26, wherein the interconnect structure includes a bump or bump material.

30. The semiconductor device of claim 26, wherein the interconnect structure includes a fusible portion and non-fusible portion.

31. A semiconductor device, comprising:

a substrate;

a conductive trace including an interconnect site formed over the substrate, the interconnect site including a width substantially equal to a width of the conductive trace away from the interconnect site;

a plurality of individual non-conductive masking patches formed over an area of the substrate interstitial around and physically separated from the interconnect site; and

a semiconductor die including an interconnect structure disposed over the interconnect site.

32. The semiconductor device of claim 31, further including a plurality of asperities formed over the interconnect structure.

33. The semiconductor device of claim 31, further including an opening formed in the conductive trace.

34. The semiconductor device of claim 33, further including the interconnect structure disposed within the opening.

35. The semiconductor device of claim 31, wherein the interconnect structure includes a tip narrower than a body of the interconnect structure and the conductive trace deforms around the tip.