Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

• US 10,388,652 B2
• Filed: 11/14/2017
• Issued: 08/20/2019
• Est. Priority Date: 11/14/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Shi, Yongiun, Sun, Lei, Economikos, Laertis, Xie, Ruilong, Liebmann, Lars, Park, Chanro, Chanemougame, Daniel, Sung, Min Gyu, Lo, Hsien-Ching, Wang, Haiting
• Primary Examiner(s): Mehta, Ratisha
• Application Number:
  US15/811,961
• Publication Number:
  US 20190148373A1
• Time in Patent Office: 644 Days
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

Claims

1. A method of forming an integrated circuit (IC) structure, the method comprising:

providing a structure including;

a plurality of fins positioned on a substrate,

a plurality of shallow trench isolations (STIs) each positioned on the substrate laterally adjacent to one of the plurality of fins, and

a masking layer positioned on the plurality of fins and the plurality of STIs;

forming a first trench in the masking layer to expose the plurality of fins, wherein the first trench extends transversely across the plurality of fins;

forming a second trench within the masking layer to expose one of the plurality of STIs, the second trench extending substantially in parallel with the plurality of fins, and wherein the second trench is positioned at a lateral end of the first trench;

forming a first opening within at least one of the exposed fins of the first trench to expose the substrate thereunder;

forming a second opening within the exposed one of the plurality of STIs of the second trench without exposing the substrate thereunder; and

forming an insulator on the exposed substrate and the exposed one of the plurality of STIs.

2. The method of claim 1, wherein forming the first trench and the second trench within the masking layer includes:

removing a portion of the masking layer over the plurality of fins and the exposed one of the plurality of STIs; and

removing a dielectric liner from the plurality of fins and one of the plurality of STIs to expose the plurality of fins or the one of the plurality of STIs thereunder.

3. The method of claim 1, further comprising conformally forming a dielectric liner on the first and second trenches before forming the first opening or the second opening.

4. The method of claim 3, wherein forming the dielectric liner substantially prevents sidewalls of the first and second trenches of the masking layer from being horizontally etched during the forming of the first opening and the second opening.

5. The method of claim 3, wherein the insulator and the dielectric liner have a same material composition.

6. The method of claim 1, wherein a depth of the first opening from an upper surface of the plurality of fins is greater than a depth of the second opening from an upper surface of the one of the plurality of STIs.

7. The method of claim 1, further comprising, after forming the insulator:

removing the masking layer to expose another portion of the plurality of fins; and

forming a metal gate over the exposed another portion of the plurality of fins.

8. A method of forming an integrated circuit (IC) structure, the method comprising:

providing a structure including;

a plurality of fins positioned on a substrate,

a plurality of shallow trench isolations (STIs) each positioned on the substrate laterally adjacent to one of the plurality of fins, and

a set of gate structures positioned on the plurality of fins and extending transversely across the plurality of fins;

removing the set of gate structures from the structure;

forming a gate coating on the structure, after removing the set of gate structures;

forming a masking layer on the gate coating, after removing the set of gate structures;

forming a first trench within the masking layer to expose a portion of one of the plurality of fins, the first trench extending transversely across the plurality of fins;

forming a second trench within the masking layer to expose one of the plurality of STIs, the second trench extending substantially in parallel with the plurality of fins, and positioned at a lateral end of the first trench;

forming a first opening within the exposed portion of one of the plurality fins, within the first trench to expose the substrate thereunder;

forming a second opening within the exposed one of the plurality of STIs of the second trench without exposing the substrate thereunder; and

forming an insulator on the exposed substrate and the exposed one of the plurality of STIs.

9. The method of claim 8, wherein forming the first trench and the second trench within the masking layer includes:

removing a portion of the masking layer over the exposed portion of one the plurality of fins and the exposed one of the plurality of STIs; and

removing a dielectric liner from the exposed portion of one of the plurality of fins and one of the plurality of STIs to expose the plurality of fins or the one of the plurality of STIs thereunder.

10. The method of claim 8, further comprising conformally forming a dielectric liner on the first and second trenches before forming the first opening or the second opening.

11. The method of claim 10, wherein the dielectric liner protects portions of the masking layer from being removed during the forming of the first opening or the second opening.

12. The method of claim 10, wherein the gate coating includes:

a gate dielectric layer; and

a high work function metal positioned on the gate dielectric layer.

13. The method of claim 8, wherein a depth of the first opening from an upper surface of the plurality of fins is greater than a depth of the second opening from an upper surface of the one of the plurality of STIs.

14. The method of claim 8, further comprising, after forming the insulator:

removing the masking layer to expose another portion of the plurality of fins; and

forming metal gate over the exposed another portion of the plurality of fins.