Semiconductor device and method of manufacturing the same

• US 10,388,661 B2
• Filed: 08/21/2017
• Issued: 08/20/2019
• Est. Priority Date: 12/19/2016
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Min Woo, Cho, Kyo Yeon
• Primary Examiner(s): Garber, Charles D
• Assistant Examiner(s): Liu, Xiaoming
• Application Number:
  US15/682,003
• Publication Number:
  US 20180175053A1
• Time in Patent Office: 729 Days
• Field of Search: None
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.

Claims

1. A semiconductor device comprising:

a tunnel insulating layer configured to enclose a channel layer;

interlayer insulating layers stacked and configured to enclose the tunnel insulating layer;

data storage layers disposed in respective spaces between the interlayer insulating layers and configured to enclose the tunnel insulating layer, each of the data storage layers being disposed in one side of the corresponding space adjacent to the tunnel insulating layer; and

conductive patterns surrounding the tunnel insulating layer with the data storage layers interposed therebetween and filling the spaces,

wherein the tunnel insulating layer has a first portion extending from each of the data storage layers to the channel layer in a first direction and a second portion extending from each of the interlayer insulating layers to the channel layer in the first direction, and

wherein the first portion is thinner than the second portion in the first direction.

2. The semiconductor device according to claim 1, wherein the data storage layers protrude further toward the tunnel insulating layer than the interlayer insulating layers.

3. The semiconductor device according to claim 1, wherein the tunnel insulating layer includes depressions which are concave toward the channel layer.

4. The semiconductor device according to claim 1, wherein each of the data storage layers is thicker than the channel layer.

5. The semiconductor device according to claim 1, wherein the tunnel insulating layer is thicker than the channel layer.

6. A semiconductor device comprising:

a channel hole including a tunnel insulating layer configured to enclose a channel layer;

interlayer insulating layers stacked and configured to enclose the tunnel insulating layer;

data storage layers disposed in respective spaces between the interlayer insulating layers and configured to enclose the tunnel insulating layer, wherein a first interface between the tunnel insulating layer and each of the data storage layers is distant from the channel layer at a smaller distance than a second interface between the tunnel insulating layer and each of the interlayer insulating layers;

blocking insulating layers disposed on the data storage layers, respectively, wherein an end portion of each of the data storage layers is completely covered by the corresponding blocking insulating layer; and

conductive patterns filling the spaces and disposed on the blocking insulating layers, respectively.

7. The semiconductor device according to claim 6, wherein each of the data storage layers is formed outside the channel hole.

8. The semiconductor device according to claim 6, wherein each of the data storage layers includes a region disposed outside the channel hole and a region disposed inside the channel hole.