Array substrate having source and drain transfer portions integrated with channel and liquid crystal display panel including same

• US 10,388,679 B2
• Filed: 01/11/2019
• Issued: 08/20/2019
• Est. Priority Date: 04/29/2016
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Wang, Zhiwu
• Primary Examiner(s): Hoang, Quoc D
• Application Number:
  US16/245,276
• Publication Number:
  US 20190148418A1
• Time in Patent Office: 221 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

An array substrate includes a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack. The active layer includes a source transfer portion and a drain transfer portion separated from the source transfer portion and a channel integrally connected to the source transfer portion and the drain transfer portion. Contact resistances between the source transfer portion, the drain transfer portion and the channel are reduced, and interface defects of the channel are reduced, so that through the source transfer portion and the drain transfer portion, an on-state current of a thin film transistor is increased and an off-state current is reduced so that is the on/off ratio is raised to improve the performance of the array substrate.

Claims

1. An comprising a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack, wherein the active layer comprises a source transfer portion and a drain transfer portion separated from the source transfer portion, and a channel integrally connected to the source transfer portion and the drain transfer portion;

wherein the source transfer portion and the drain transfer portion are formed at a first predetermined temperature and the channel is formed at a second predetermined temperature, the first predetermined temperature being higher than the second predetermined temperature;

wherein the active layer, source transfer portion, and the drain transfer portion are simultaneously formed of a layer of a predetermined material, which is disposed on the gate insulating layer and comprises a first region and a second region respectively at two ends of the layer of the predetermined material and a third region located between and connected to the first and second regions, wherein surface parts of the first region and the second region that are adjacent to a surface of the layer of the predetermined material distant from the gate insulating layer are formed into the source transfer portion and the drain transfer portion at the first predetermined temperature, respectively, and the third region is formed, at the second predetermined temperature, into the channel that connects between the surface parts of the first and second regions that are formed into the source and drain transfer portions, wherein the surface parts of the first region and the second region that are formed into the source transfer portion and drain transfer portion are integral portions of the metal oxide layer and are integrally connected with the channel;

wherein a barrier layer is disposed on the surface of the layer of the predetermined material that is distant from the gate insulating layer and has a first through hole and a second through hole separate from the first through hole, and a light shielding area between the first through hole and the second through hole, wherein the first through hole and the second through hole expose the source transfer portion and the drain transfer portion respectively and the light shielding area covers the channel, such that laser irradiating on the barrier layer is allowed to pass directly through the first and second through holes to cause the first predetermined temperature in the source transfer portion and the drain transfer portion and the light shielding area absorbs and converts a part of the laser irradiating on the barrier into heat that is transferred to the channel to cause the second predetermined temperature in the channel.

2. The array substrate according to claim 1, further comprising a source electrode and a drain electrode disposed on the barrier layer, wherein the source electrode is connected to the source transfer portion through the first through hole, and the drain electrode is connected to the drain transfer portion through the second through hole.

3. The array substrate according to claim 1, wherein the substrate comprises a plastic layer and a buffer layer stacked on the plastic layer, the gate electrode being stacked on the buffer layer and opposite to the plastic layer.

4. The array substrate according to claim 1, wherein the predetermined material comprises an oxide semiconductor.

5. The array substrate according to claim 4, wherein the source transfer portion and the drain transfer portion that are located at the two ends of the active layer are formed through laser crystallization.

6. A liquid crystal display panel, comprising an array substrate that comprises a substrate, a gate electrode, a gate insulating layer and an active layer formed in sequence in a stack, wherein the active layer comprises a source transfer portion and a drain transfer portion separated from the source transfer portion, and a channel integrally connected to the source transfer portion and the drain transfer portion;

wherein the source transfer portion and the drain transfer portion are formed at a first predetermined temperature and the channel is formed at a second predetermined temperature, the first predetermined temperature being higher than the second predetermined temperature;

wherein the active layer, source transfer portion, and the drain transfer portion are simultaneously formed of a layer of a predetermined material, which is disposed on the gate insulating layer and comprises a first region and a second region respectively at two ends of the layer of the predetermined material and a third region located between and connected to the first and second regions, wherein surface parts of the first region and the second region that are adjacent to a surface of the layer of the predetermined material distant from the gate insulating layer are formed into the source transfer portion and the drain transfer portion at the first predetermined temperature, respectively, and the third region is formed, at the second predetermined temperature, into the channel that connects between the surface parts of the first and second regions that are formed into the source and drain transfer portions, wherein the surface parts of the first region and the second region that are formed into the source transfer portion and drain transfer portion are integral portions of the metal oxide layer and are integrally connected with the channel;

wherein a barrier layer is disposed on the surface of the layer of the predetermined material that is distant from the gate insulating layer and has a first through hole and a second through hole separate from the first through hole, and a light shielding area between the first through hole and the second through hole, wherein the first through hole and the second through hole expose the source transfer portion and the drain transfer portion respectively and the light shielding area covers the channel, such that laser irradiating on the barrier layer is allowed to pass directly through the first and second through holes to cause the first predetermined temperature in the source transfer portion and the drain transfer portion and the light shielding area absorbs and converts a part of the laser irradiating on the barrier into heat that is transferred to the channel to cause the second predetermined temperature in the channel.

7. The liquid crystal display panel according to claim 6, wherein the array substrate further comprises a source electrode and a drain electrode disposed on the barrier layer, the source electrode being connected to the source transfer portion through the first through hole, the drain electrode being connected to the drain transfer portion through the second through hole.

8. The liquid crystal display panel according to claim 6, wherein the substrate comprises a plastic layer and a buffer layer stacked on the plastic layer, the gate electrode being stacked on the buffer layer and opposite to the plastic layer.

9. The liquid crystal display panel according to claim 6, wherein the predetermined material comprises an oxide semiconductor.

10. The liquid crystal display panel according to claim 9, wherein the source transfer portion and the drain transfer portion that are located at the two ends of the active layer are formed through laser crystallization.