Electronic device package

• US 10,388,700 B2
• Filed: 05/23/2017
• Issued: 08/20/2019
• Est. Priority Date: 07/22/2016
• Status: Active Grant

• Current Assignee: E Ink Holdings Incorporated
• Original Assignee: E Ink Holdings Incorporated
• Inventors: Chang, Kuo-Yen, Yeh, Chia-Chun, Cheng, Kuo-Hsing, Wu, Hsing-Yi
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/603,440
• Publication Number:
  US 20180026078A1
• Time in Patent Office: 819 Days
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/88 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements

Abstract

An electronic device package includes a carrying board, an electronic device, a first insulating layer, and a barrier layer. The carrying board includes a central area, an inner edge area, and an outer edge area. The inner edge area is located between the central area and the outer edge area. The electronic device is located in the central area. The first insulating layer is located on the carrying board and overlapped with the electronic device and extends from the central area to the inner edge area. The barrier layer is located on the carrying board. Here, the barrier layer includes a sidewall contact portion and an extending portion. The sidewall contact portion surrounds a side surface of the first insulating layer, and the extending portion extends from the sidewall contact portion to the outer edge area in a direction away from the first insulating layer.

Claims

1. An electronic device package comprising:

a carrying board comprising a central area, an inner edge area, and an outer edge area, the inner edge area being located between the central area and the outer edge area;

an electronic device located in the central area of the carrying board;

a first insulating layer located on the carrying board and overlapped with the electronic device, the first insulating layer extending from the central area to the inner edge area;

a barrier layer located on the carrying board, the barrier layer comprising a sidewall contact portion and an extending portion, the sidewall contact portion surrounding a side surface of the first insulating layer, the extending portion extending from the sidewall contact portion to the outer edge area in a direction away from the first insulating layer; and

a sidewall block structure located in the inner edge area, the sidewall block structure penetrating the first insulating layer and constituting a wall-like structure, wherein a top of the sidewall block structure is covered by the barrier layer and a portion of the first insulating layer is located between the sidewall block structure and the sidewall contact portion of the barrier layer.

2. The electronic device package of claim 1, wherein the barrier layer further comprises a cover portion, the cover portion extends from the sidewall contact portion in a direction away from the extending portion and covers the first insulating layer, and the cover portion exposes the central portion.

3. The electronic device package of claim 1, wherein the electronic device comprises a gate, a source, a drain, and an organic semiconductor channel layer, an area of the gate is overlapped with an area of the organic semiconductor channel layer, the first insulating layer is located between the gate and the organic semiconductor channel layer, and the source and the drain are connected to the organic semiconductor channel layer.

4. The electronic device package of claim 1, wherein the sidewall contact portion covers the side surface of the first insulating layer.

5. The electronic device package of claim 1, further comprising a second insulating layer, the first insulating layer being located between the second insulating layer and the carrying board.

6. The electronic device package of claim 5, wherein an area of the second insulating layer exceeds the first insulating layer and has a sidewall portion, and the sidewall portion is located between the side surface of the first insulating layer and the sidewall contact portion.

7. The electronic device package of claim 1, wherein the sidewall block structure comprises a plurality of sub-block structures stacked together in a direction perpendicular to the carrying board.

8. The electronic device package of claim 7, wherein a material of each of the sub-block structures comprises metal.

9. The electronic device package of claim 1, wherein the extending portion of the barrier layer has a concave-convex surface at an upper side away from the carrying board.

10. The electronic device package of claim 9, wherein the concave-convex surface has a sawtooth shape, a micro-cup shape, a ladder shape, or a combination of any of the above shapes.

11. The electronic device package of claim 1, wherein a material of the barrier layer is SiNx, SiOx, or multiple layers of SiNx/SiOx thin films.

12. The electronic device package of claim 1, further comprising:

an organic buffer layer located between the electronic device and the carrying board;

a bottom barrier layer located between the organic buffer layer and the carrying board;

a display medium layer located on the electronic device, wherein the display medium layer and the electronic device are electrically connected to each other and configured to display images; and

a protection layer located on the display medium layer.

13. The electronic device package of claim 12, wherein the extending portion of the barrier layer is in contact with the bottom barrier layer.

14. The electronic device package of claim 12, wherein the sidewall contact portion of the barrier layer covers a side surface of the organic buffer layer.

15. An electronic device package comprising:

a carrying board comprising a central area and an edge area;

an electronic device located in the central area of the carrying board, wherein the electronic device comprises a gate, a source, a drain, and an organic semiconductor channel layer connecting to the source and the drain;

a plurality of insulating layers located on the carrying board and overlapped with the electronic device, the insulating layers respectively extending from the central area to the edge area, wherein one of the insulating layers separates the gate from the organic semiconductor channel layer; and

a sidewall block structure located in the edge area, the sidewall block structure penetrating the insulating layers and constituting a stopper wall, wherein the sidewall block structure comprises a plurality of sub-block structures stacked together in a direction perpendicular to the carrying board, and

wherein at least two layers of the sub-block structures are made by metal, and one of the sub-block structures and one of the gate, the source and the drain are formed by the same layer.

16. The electronic device package of claim 15, wherein one of the sub-block structures is electrically connected to the electronic device.

17. The electronic device package of claim 15, wherein a material of each of the sub-block structures comprises metal.

18. The electronic device package of claim 17, wherein the sidewall block structure is electrically floating.

19. The electronic device package of claim 15, wherein the insulating layers comprise a first insulating layer and a second insulating layer, an area of the gate is overlapped with an area of the organic semiconductor channel layer, the first insulating layer is located between the gate and the organic semiconductor channel layer, and the first insulating layer is located between the second insulating layer and the carrying board.

20. The electronic device package of claim 15, further comprising:

an organic buffer layer located between the electronic device and the carrying board;

a bottom barrier layer located between the organic buffer layer and the carrying board;

a display medium layer located on the electronic device, wherein the display medium layer and the electronic device are electrically connected to each other and configured to display images; and

a protection layer located on the display medium layer.