Nanosheet field-effect transistors including a two-dimensional semiconducting material

• US 10,388,732 B1
• Filed: 05/30/2018
• Issued: 08/20/2019
• Est. Priority Date: 05/30/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Frougier, Julien, Xie, Ruilong, Loubet, Nicolas, Cheng, Kangguo, Li, Juntao
• Primary Examiner(s): Schoenholtz, J. E.
• Application Number:
  US15/992,942
• Time in Patent Office: 447 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/02568 Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/041 Making n- or p-doped regions
• CPC Class Codes: H01L 21/044 Conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/423 with high-energy radiation
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/778 : with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.

Claims

1. A structure for a field-effect transistor, the structure comprising:

a plurality of channel layers arranged in a layer stack;

a source/drain region connected with the plurality of channel layers; and

a gate structure including a plurality of sections that respectively surround the plurality of channel layers,

wherein the plurality of channel layers are comprised of a two-dimensional semiconducting material, and the source/drain region is comprised of the two-dimensional semiconducting material.

2. The structure of claim 1 wherein the two-dimensional semiconducting material is a transition metal dichalcogenide.

3. The structure of claim 1 wherein the two-dimensional semiconducting material is molybdenum disulphide, hafnium disulfide, zirconium disulfide, tungsten disulfide, tin sulfide, or tungsten diselenide.

4. The structure of claim 1 wherein the two-dimensional semiconducting material is graphene.

5. The structure of claim 1 wherein the two-dimensional semiconducting material of the source/drain region contains a dopant effective to increase an electrical conductivity of the two-dimensional semiconducting material of the source/drain region.

6. The structure of claim 1 further comprising:

a contact coupled with the two-dimensional semiconducting material of the source/drain region.

7. The structure of claim 6 wherein the two-dimensional semiconducting material of the source/drain region contains a dopant effective to increase electrical conductivity.

8. The structure of claim 1 wherein each channel layer includes a first section and a second section that are separated by an air gap.

9. The structure of claim 1 wherein each channel layer includes a first section and a second section spaced from the first section, and the structure further comprising:

a dielectric layer arranged between the first section and the second section of each channel layer.

10. The structure of claim 1 wherein each channel layer has a thickness of one nanometer to three nanometers.

11. The structure of claim 1 wherein each channel layer is a sheet including a monolayer of atoms.

20. The structure of claim 1 wherein the layer stack has a sidewall, and the two-dimensional semiconducting material of the source/drain region is arranged as a conformal coating on the sidewall of the layer stack.

12. A method of forming a field-effect transistor, the method comprising:

forming a plurality of nanosheet channel layers arranged in a layer stack;

forming a gate structure including a plurality of sections that respectively surround the plurality of nanosheet channel layers;

after forming the gate structure, removing the plurality of nanosheet channel layers to form a plurality of spaces between the plurality of sections of the gate structure; and

depositing a two-dimensional semiconducting material in the plurality of spaces between the plurality of sections of the gate structure to form a plurality of replacement channel layers.

13. The method of claim 12 wherein the two-dimensional semiconducting material is a transition metal dichalcogenide.

14. The method of claim 12 wherein the two-dimensional semiconducting material is deposited as a conformal coating on a sidewall of the layer stack to provide a source/drain region that is connected with the plurality of replacement channel layers.

15. The method of claim 14 further comprising:

introducing a dopant by a plasma doping process into the two-dimensional semiconducting material of the source/drain region that is effective to increase an electrical conductivity of the two-dimensional semiconducting material of the source/drain region.

16. The method of claim 15 further comprising:

forming a contact coupled with the two-dimensional semiconducting material of the source/drain region.

17. The method of claim 12 wherein each space is partially filled by a first section and a second section of the two-dimensional semiconducting material, and an air gap is arranged in a portion of each space between the first section and the second section of the two-dimensional semiconducting material.

18. The method of claim 12 wherein each space is partially filled by a first section and a second section of the two-dimensional semiconducting material, and the method further comprises:

depositing a dielectric layer in a portion of each space that is arranged between the first section and the second section of the two-dimensional semiconducting material.

19. The method of claim 12 wherein each channel layer is a sheet including a monolayer of atoms.