Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) devices having an optimization layer

• US 10,388,737 B2
• Filed: 05/22/2017
• Issued: 08/20/2019
• Est. Priority Date: 05/23/2016
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Bolotnikov, Alexander Viktorovich, Losee, Peter Almern
• Primary Examiner(s): Jang, Bo B
• Application Number:
  US15/601,754
• Publication Number:
  US 20170338303A1
• Time in Patent Office: 820 Days
• Field of Search: 257 76, 257 77, 257E21054, 257E21055, 257E21065
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

Claims

1. A device, comprising:

a plurality of device cells at least partially disposed in a semiconductor device layer having a first conductivity type, wherein each device cell of the plurality of device cells comprises;

a drift layer having the first conductivity type;

an optimization layer extending from a surface of the semiconductor device layer to the drift layer and having the first conductivity type, wherein the optimization layer has an average doping concentration that is greater than an average doping concentration of the drift layer;

a source region having the first conductivity type at least partially disposed within the optimization layer;

a channel region having a second conductivity type at least partially disposed within the optimization layer adjacent to the source region; and

a junction field-effect transistor (JFET) region having the first conductivity type and a second doping concentration disposed within the optimization layer between the channel regions of the plurality of device cells, wherein the JFET region has a parallel JFET width between a well region of the device cell and a parallel portion of a well region of a neighboring device cell; and

a plurality of shielding regions disposed within the optimization layer (SROLs) having the first conductivity type and a first doping concentration, wherein the plurality of SROLs are at least partially disposed within a portion of the JFET region between the channel regions of neighboring device cells of the plurality of device cells, wherein the optimization layer has a retrograde doping profile that increases in doping concentration between a first dopant concentration at the surface of the semiconductor device layer and a second dopant concentration at a first depth from the surface of the semiconductor device layer, and maintains the second dopant concentration between the first depth and the drift region of the semiconductor layer, wherein the second dopant concentration is between four (4) and ten (10) times greater than the first dopant concentration.

2. The device of claim 1, wherein the first depth is between 0.15 μ

m and 0.3 μ

m, the first dopant concentration is between 5×

10¹⁵ cm<sup>−

3</sup> and 5×

10¹⁶ cm<sup>−

3</sup>, and the second dopant concentration is between 5×

10¹⁶ cm<sup>−

3</sup> and 1×

10¹⁷ cm³.

3. The device of claim 1, wherein the second dopant concentration is less than 20% of an average dopant concentration of the channel region.

4. The device of claim 1, wherein the semiconductor device layer is a silicon carbide (SiC) semiconductor device layer.

5. The device of claim 1, wherein each of the plurality of SROLs overlaps with a portion of the well region of at least one device cell of the plurality of device cells.

6. The device of claim 5, wherein each of the plurality of SROLs overlaps with a portion of the well regions of at least two device cells of the plurality of device cells.

7. The device of claim 6, wherein each of the plurality of SROLs overlaps with a portion of the well regions of at least three device cells of the plurality of device cells.

8. The device of claim 5, wherein the plurality of SROLs further overlaps with a portion of the source regions of the plurality of device cells.

9. The device of claim 1, wherein the plurality of SROLs do not overlap with the well regions of the plurality of device cells.

10. The device of claim 1, wherein the plurality of SROLs occupies between approximately 1% and approximately 30% of an area of each of the plurality of device cells.

11. The device of claim 10, wherein the plurality of SROLs occupies between approximately 5% and approximately 20% of the area of each of the plurality of device cells.

12. The device of claim 11, wherein the plurality of SROLs occupies between approximately 7% and approximately 15% of the area each of the plurality of device cells.

13. The device of claim 1, wherein each of the plurality of SROLs comprises a respective width that is between approximately 0.5 μ

m and approximately 5 μ

m.

14. The device of claim 13, wherein the respective width is between approximately 1 μ

m and approximately 3 μ

m.

15. The device of claim 1, wherein the plurality of SROLs has a substantially triangular, circular, ovular, hexagonal, rectangular, or irregular shape.

16. The device of claim 1, wherein the device is a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or an insulated base MOS-controlled thyristor (IBMCT).

17. The device of claim 1, wherein the average doping concentration of the optimization layer is between two (2) and fifteen (15) times greater than the average doping concentration of the drift layer.

18. The device of claim 1, wherein each of the plurality of SROLs has a doping concentration that is substantially the same as a doping concentration of the drift layer.