Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure

• US 10,388,747 B1
• Filed: 03/28/2018
• Issued: 08/20/2019
• Est. Priority Date: 03/28/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Prindle, Christopher M., Bourjot, Emilie, Economikos, Laertis
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US15/938,510
• Time in Patent Office: 510 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One illustrative integrated circuit product disclosed herein includes a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, the T-shaped portion of the gate structure comprising a relatively wider upper portion and a relatively narrower lower portion, and first and second conductive source/drain structures positioned adjacent opposite sidewalls of the T-shaped gate structure. In this example, the product also includes first and second air gaps positioned adjacent opposite sidewall of the T-shaped gate structure, wherein each of the air gaps is positioned between at least the lower portion of one of the sidewalls of the T-shaped gate structure and the adjacent conductive source/drain structure.

Claims

1. An integrated circuit product, comprising:

a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, said T-shaped gate structure comprising an upper portion and a lower portion, wherein said upper portion has a greater lateral width in a current transport direction of said transistor device than said lower portion;

first and second conductive source/drain structures positioned adjacent opposite sidewalls of said T-shaped gate structure; and

first and second air gaps positioned adjacent opposite sidewalls of said T-shaped gate structure, wherein each of said air gaps is positioned between at least said lower portion of said T-shaped gate structure and adjacent conductive source/drain structures.

2. The integrated circuit product of claim 1, further comprising a conductive gate contact structure that is conductively coupled to an upper surface of said T-shaped gate structure, wherein an entirety of said conductive gate contact structure is positioned vertically above said active region of said transistor device.

3. The integrated circuit product of claim 1, wherein, in a direction corresponding to a gate width direction of said transistor device, said T-shaped gate structure has a non-recessed portion with a first upper surface and a recessed portion with a second upper surface, said second upper surface being positioned at a level below a level of said first upper surface, and wherein the product further comprises a conductive gate contact structure that is conductively coupled to said T-shaped gate structure wherein substantially all of the physical contact between the conductive gate contact structure and the T-shaped gate structure occurs at said first upper surface of said T-shaped gate structure.

4. The integrated circuit product of claim 1, wherein said first and second air gaps constitute a substantially continuous air space that extends around an entire perimeter of said T-shaped gate structure.

5. The integrated circuit product of claim 2, wherein, at a location adjacent said conductive gate contact structure, each of said first and second conductive source/drain structures has an upper surface that is positioned at a level that is below a level of an upper surface of said upper portion of said T-shaped gate structure.

6. The integrated circuit product of claim 1, further comprising a conductive source/drain contact structure that is conductively coupled to an upper surface of a conductive source/drain structure of another transistor device, wherein said upper surface of said conductive source/drain structure of said another transistor device is substantially planar with an upper surface of said upper portion of said T-shaped gate structure.

7. The integrated circuit product of claim 1, wherein, in a direction corresponding to a gate width direction of said transistor device, at least one of said first and second conductive source/drain structures has a non-recessed portion with a first upper surface and a recessed portion with a second upper surface, said second upper surface being positioned at a level below a level of said first upper surface, and wherein the product further comprises a conductive source/drain contact structure that is conductively coupled to said at least one of said first and second conductive source/drain structures, wherein substantially all of the physical contact between the conductive source/drain contact structure and said at least one of said first and second conductive source/drain structure occurs at said first upper surface of said at least one of said first and second conductive source/drain structures.

8. The integrated circuit product of claim 1, wherein a bottom surface of each of said first and second air gaps is defined by an upper surface of a sidewall spacer positioned on said lower portion of said T-shaped gate structure.

9. The integrated circuit product of claim 8, wherein said sidewall spacer is a single sidewall spacer comprised of a single material.

10. The integrated circuit product of claim 8, wherein said sidewall spacer comprises first and second sidewall spacers made of different materials.

11. The integrated circuit product of claim 1, wherein said first and second air gaps are formed in a sidewall spacer positioned on opposing sidewalls of said lower portion of said T-shaped gate structure.

12. An integrated circuit product, comprising:

a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, said T-shaped gate structure comprising an upper portion and a lower portion, wherein said upper portion has a greater lateral width in a current transport direction of said transistor device than said lower portion, and wherein, in a direction corresponding to a gate width direction of said transistor device, said T-shaped gate structure has a non-recessed portion with a first upper surface and a recessed portion with a second upper surface, said second upper surface being positioned at a level below a level of said first upper surface;

first and second conductive source/drain structures positioned adjacent opposite sidewalls of said T-shaped gate structure;

first and second air gaps positioned adjacent opposite sidewalls of said T-shaped gate structure, wherein each of said air gaps is positioned between at least said lower portion of said T-shaped gate structure and adjacent conductive source/drain structures; and

a conductive gate contact structure that is conductively coupled to said T-shaped gate structure, wherein at a location adjacent said conductive gate contact structure, each of said conductive source/drain structures has an upper surface that is positioned at a level that is below a level of the first upper surface of said non-recessed portion of said T-shaped gate structure.

13. The integrated circuit product of claim 12, wherein said first and second air gaps constitute a substantially continuous air space that extends around an entire perimeter of said T-shaped gate structure.

14. The integrated circuit product of claim 12, wherein an entirety of said conductive gate contact structure is positioned vertically above said active region and wherein substantially all of the physical contact between the conductive gate contact structure and the T-shaped gate structure occurs at said first upper surface of said non-recessed portion of the T-shaped gate structure.

15. The integrated circuit product of claim 14, further comprising a conductive source/drain contact structure that is conductively coupled to an upper surface of a conductive source/drain structure of another transistor device, wherein said upper surface of said conductive source/drain structure of said another transistor device is substantially planar with the first upper surface of said non-recessed portion of said T-shaped gate structure.

16. A method, comprising:

forming a gate for a transistor device, said gate comprising a sacrificial gate structure, a sidewall spacer positioned adjacent said sacrificial gate structure and a gate cap positioned above said sacrificial gate structure;

forming first and second conductive source/drain structures adjacent said sidewall spacer on opposite sidewalls of said sacrificial gate structure;

performing an etching process to reduce a lateral thickness of an upper portion of said sidewall spacer that is located above an upper surface of said sacrificial gate structure;

removing said sacrificial gate structure to form a replacement gate cavity having an upper portion with a first lateral width and a lower portion with a second lateral width that is less than said first lateral width, said first lateral width being defined by said upper portion of said sidewall spacer with said reduced lateral width;

forming a replacement gate structure in said replacement gate cavity, said replacement gate structure having a T-shaped configuration and comprising an upper portion and a lower portion, wherein said upper portion has a greater lateral width in a current transport direction of said transistor device than said lower portion;

performing an etching process to remove said upper portion of said sidewall spacer and at least a portion of any remaining portion of said sidewall spacer so as to form a space between a lower portion of said T-shaped gate structure and each of said first and second conductive source/drain structures; and

forming a second spacer adjacent said T-shaped gate structure, said second spacer comprising at least first and second air gaps within said second spacer, said first and second air gaps being positioned between at least said lower portion of said T-shaped gate structure and adjacent conductive source/drain structures.

17. The method of claim 16, wherein forming said second spacer comprises performing a conformal deposition process so as to deposit a layer of second spacer material that only partially fills spaces between said T-shaped gate structure and said first and second conductive source/drain structures.

18. The method of claim 16, further comprising forming a conductive gate contact structure that is conductively coupled to an upper surface of said T-shaped gate structure, wherein an entirety of said conductive gate contact structure is positioned vertically above an active region of said transistor device.

19. The method of claim 18, wherein, prior to forming said conductive gate contact structure, the method comprises performing a recess etching process on each of said first and second conductive source/drain structures such that they have a recessed upper surface at a location adjacent said conductive gate contact structure, said recessed upper surface being at a level that is below a level of said upper surface of said T-shaped gate structure.

20. The method of claim 16, wherein said first and second air gaps constitute a substantially continuous air space that extends around an entire perimeter of said T-shaped gate structure.