Stacked nanosheets with self-aligned inner spacers and metallic source/drain

• US 10,388,755 B1
• Filed: 06/04/2018
• Issued: 08/20/2019
• Est. Priority Date: 06/04/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Choonghyun, Cheng, Kangguo, Li, Juntao
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US15/996,922
• Time in Patent Office: 442 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78621 : with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. A metal-doped insulator layer is in contact with sidewalls of the channel layers. The metal-doped insulator layer is annealed to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers. The metal-doped insulator layer is etched back to form inner spacers. Source/drain regions are formed in contact with the metallic layer. The sacrificial layers are etched away and a gate stack is formed on and around the channel layers.

Claims

1. A method for forming a semiconductor device, comprising:

forming a stack of alternating channel layers and sacrificial layers;

recessing the sacrificial layers relative to the channel layers;

depositing a metal-doped insulator layer in contact with sidewalls of the channel layers;

annealing the metal-doped insulator layer to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers;

etching back the metal-doped insulator layer to form inner spacers;

forming source/drain regions in contact with the metallic layer;

etching away the sacrificial layers; and

forming a gate stack on and around the channel layers.

2. The method of claim 1, wherein the channel layers are formed from germanium and the metal-doped insulator layer is formed from metal-doped germanium oxide.

3. The method of claim 2, wherein the sacrificial layers are formed from gallium arsenide.

4. The method of claim 1, wherein the source/drain regions are formed from a metal.

5. The method of claim 1, further comprising doping exposed portions of the channel layers after recessing the sacrificial layers.

6. The method of claim 5, wherein doping the exposed portions comprises a process selected from the group consisting of tilted ion implantation, monolayer doping, and plasma doping.

7. The method of claim 1, further comprising:

depositing a dummy gate on the stack of alternating channel layers and sacrificial layers before recessing the sacrificial layers; and

etching away the dummy gate after forming the source/drain regions and before etching away the sacrificial layers.

8. A method for forming a semiconductor device, comprising:

forming a stack of alternating channel layers and sacrificial layers;

recessing the sacrificial layers relative to the channel layers;

depositing a metal-doped insulator layer in contact with sidewalls of the channel layers;

annealing the metal-doped insulator layer to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers;

etching away the metal-doped insulator layer;

depositing a dielectric material after etching away the metal-doped insulator layer to form inner spacers;

forming source/drain regions in contact with the metallic layer;

etching away the sacrificial layers; and

forming a gate stack on and around the channel layers.

9. The method of claim 8, wherein the channel layers are formed from germanium and the metal-doped insulator layer is formed from metal-doped germanium oxide.

10. The method of claim 9, wherein the sacrificial layers are formed from gallium arsenide.

11. The method of claim 8, wherein the source/drain regions are formed from a metal.

12. The method of claim 8, further comprising doping exposed portions of the channel layers after recessing the sacrificial layers.

13. The method of claim 12, wherein doping the exposed portions comprises a process selected from the group consisting of tilted ion implantation, monolayer doping, and plasma doping.

14. The method of claim 8, further comprising:

depositing a dummy gate on the stack of alternating channel layers and sacrificial layers before recessing the sacrificial layers; and

etching away the dummy gate after forming the source/drain regions and before etching away the sacrificial layers.

15. The method of claim 8, wherein the inner spacers are formed from a low-k dielectric.