Floating-shield triple-gate MOSFET

• US 10,388,783 B2
• Filed: 02/17/2016
• Issued: 08/20/2019
• Est. Priority Date: 02/17/2016
• Status: Active Grant

• Current Assignee: Polar Semiconductor, LLC (Sanken Electric Co., Ltd.)
• Original Assignee: Polar Semiconductor, LLC (Sanken Electric Co., Ltd.)
• Inventors: Rankila, Don
• Primary Examiner(s): Hsieh, Hsin Yi
• Application Number:
  US15/045,984
• Publication Number:
  US 20170236934A1
• Time in Patent Office: 1,280 Days
• Field of Search: 257330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.

Claims

1. A trench MOSFET comprising:

a semiconductor die including a substrate, an active device region formed upon the substrate, and an interconnection region formed upon the active device region, the active device region and the interconnection region separated by an interface surface;

a pair of trenches formed in the active device region, each of the trenches extending from the interface surface to a dielectric trench bottom, the pair of trenches laterally separated from one another by an intervening semiconductor pillar;

a conductive gate located within each of the trenches and separated from the intervening semiconductor pillar by a gate dielectric;

a first conductive field plate located within each of the trenches, the first conductive field plate electrically connected to a biasing circuit net in the interconnection region, the first conductive field plate extending to a first depth location below the conductive gate, the first conductive field plate laterally separated from the intervening semiconductor pillar by a dielectric trench sidewall;

a second conductive field plate located within each of the trenches, the second conductive field plate extending to a second depth location below the first conductive field plate and separated from the first conductive field plate by an intervening dielectric layer, the second conductive field plate floated but capacitively coupled via the intervening dielectric layer to the first conductive field plate, the second conductive field plate laterally separated from the intervening semiconductor pillar by the dielectric trench sidewall;

a source region in the intervening semiconductor pillar, the source region abutting each of the trenches;

a body region in the intervening semiconductor pillar, the body region abutting each of the trenches; and

a drain region in the intervening semiconductor pillar contiguously extending from the body region to the substrate, wherein the drain region has a dopant concentration that varies from a drain/body interface to the substrate,

wherein configuration of the first and second conductive field plates, the intervening dielectric layer, the dielectric trench sidewall, and the dopant concentration in the drain region causes, under predetermined maximum bias conditions, first and second local maxima of the electric field in the drain region located proximate the drain/body interface and the dielectric trench bottom, respectively, to be substantially equal in magnitude.

2. The trench MOSFET of claim 1, wherein a lateral distance separates the pair of trenches and defines a width of the intervening semiconductor pillar, the lateral distance being less than a predetermined distance such that when the drain region is biased to a first specified voltage and the first conductive field plate is biased to a second specified voltage, the drain region between the pair of trenches is depleted of majority carriers throughout the lateral distance.

3. The trench MOSFET of claim 1, wherein the source region is discontiguous in the intervening semiconductor pillar.

4. The trench MOSFET of claim 1, wherein the drain region contiguously extends from the body region to the substrate and is junctionless from the body region to the substrate.

5. The trench MOSFET of claim 1, wherein the intervening semiconductor pillar extends a first vertical distance from the drain/body interface to a third depth location laterally adjacent to the dielectric trench bottom is separated into an upper field-plate controlled portion and a lower field-plate controlled portion, the upper field-plate controlled portion vertically extending a second vertical distance from the drain/body interface to a fourth depth location laterally adjacent to a bottom of the first conductive field plate, the lower field-plate controlled portion vertically extending a third vertical distance from the fourth depth location to a fifth depth location laterally adjacent to a bottom of the second conductive field plate.

6. The trench MOSFET of claim 5, wherein a ratio of the second vertical distance to the first vertical distance is between 0.3 and 0.7.

7. The trench MOSFET of claim 6, wherein a ratio of the second vertical distance to the first vertical distance is between 0.4 and 0.6.

8. The trench MOSFET of claim 1, wherein the body region is electrically connected to the biasing circuit net.

9. The trench MOSFET of claim 1, wherein the source region is electrically connected to the biasing circuit net.

10. A trench MOSFET comprising:

a semiconductor die having a lower substrate region, an intermediate active region, and an upper interconnection region, the intermediate active region having a top interface surface delineating a plane separating the intermediate active region from the upper interconnection region, wherein the intermediate active region is formed of alternating series of semiconductor pillars and longitudinal trenches,

wherein each of the semiconductor pillars has a source region, a body region, and a drain region contiguously extending form the body region to the lower substrate region, wherein the drain region has a dopant concentration that varies from a drain/body interface to the lower substrate region, and

wherein each of the longitudinal trenches vertically extends from the top interface surface to a dielectric trench bottom, each of the longitudinal trenches having conductive gates on either of two lateral ends, the conductive gates separated from the body regions of adjacent semiconductor pillars by a gate dielectric, each of the longitudinal trenches having an upper conductive field plate and a lower conductive field plate, the upper and lower conductive field plates separated from the drain regions of adjacent semiconductor pillars by dielectric sidewalls, the upper and lower conductive field plates in each of the longitudinal trenches vertically aligned to one another, the upper conductive field plate being biased by electrical conduction with a circuit net in the upper interconnection region, the lower conductive field plate floated and capacitively coupled via an intervening dielectric layer to the upper conductive field plate,

wherein configuration of the upper and lower conductive field plates, the intervening dielectric layer, the dielectric sidewall, and the dopant concentration in the drain region causes, under predetermined maximum bias conditions, first and second local maxima of the electric field in the drain region located proximate the drain/body interface and the dielectric trench bottom, respectively, to be substantially equal in magnitude.

11. The trench MOSFET of claim 10, wherein the drain region of each of the semiconductor pillars extends a first vertical distance from the drain/body interface to a first depth location laterally adjacent to the dielectric trench bottom of each of the longitudinal trenches, the drain region separated into an upper field-plate controlled portion and a lower field-plate controlled portion, the upper field-plate controlled portion vertically extending a second vertical distance from the drain/body interface to a second depth location laterally adjacent to a bottom of the upper conductive field plate, the lower field-plate controlled portion vertically extending a third vertical distance from the second depth location laterally adjacent to the bottom of the upper conductive field plate to a third depth location laterally adjacent to a bottom of the lower conductive field plate.

12. The trench MOSFET of claim 11, wherein a ratio of the second vertical distance to the first vertical distance is between 0.3 and 0.7.

13. The trench MOSFET of claim 11, wherein a ratio of the second vertical distance to the first vertical distance is between 0.4 and 0.6.