Gate-all-around fin device

• US 10,388,793 B2
• Filed: 11/21/2017
• Issued: 08/20/2019
• Est. Priority Date: 11/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campi, Jr., John B., Gauthier, Jr., Robert J., Mishra, Rahul, Mitra, Souvick, Muhammad, Mujahid
• Primary Examiner(s): Pham, Long
• Application Number:
  US15/819,486
• Publication Number:
  US 20180076328A1
• Time in Patent Office: 637 Days
• Field of Search: None
• CPC Class Codes: B29C 37/0025 Applying surface layers, e.g. coatings, decorative layers, printed layers, to articles during shaping, e.g. in-mould printing moulding on preformed layers as inserts B29C70/68; applying fluent material to surfaces in general B05
• CPC Class Codes: B29C 48/21 the layers being joined at their surfaces
• CPC Class Codes: B29C 48/49 using two or more extruders to feed one die or nozzle
• CPC Class Codes: B29K 2023/12 PP, i.e. polypropylene
• CPC Class Codes: B29K 2105/16 Fillers
• CPC Class Codes: B29K 2507/04 Carbon
• CPC Class Codes: B29K 2995/0005 Conductive
• CPC Class Codes: B29K 2995/0007 Insulating
• CPC Class Codes: B29L 2009/003 comprising a metal layer
• CPC Class Codes: B29L 2009/005 coated
• CPC Class Codes: B29L 2031/34 Electrical apparatus, e.g. sparking plugs or parts thereof
• CPC Class Codes: B32B 2262/106 Carbon fibres, e.g. graphite fibres
• CPC Class Codes: B32B 2264/105 Metal
• CPC Class Codes: B32B 2264/12 Mixture of at least two particles made of different materials
• CPC Class Codes: B32B 2270/00 Resin or rubber layer containing a blend of at least two different polymers
• CPC Class Codes: B32B 2274/00 Thermoplastic elastomer material
• CPC Class Codes: B32B 2307/202 Conductive
• CPC Class Codes: B32B 2307/204 Di-electric
• CPC Class Codes: B32B 2307/206 Insulating
• CPC Class Codes: B32B 2307/518 bi-axially
• CPC Class Codes: B32B 2307/732 : Dimensional properties
• CPC Class Codes: B32B 2457/16 : Capacitors
• CPC Class Codes: B32B 27/00 : Layered products comprising a layer of synthetic resin fibrous or filamentary layer made of a synthetic resin B32B5/02; particulate layer made of a synthetic resin B32B5/16; foamed layer made of a synthetic resin B32B5/18
• CPC Class Codes: B32B 27/08 : of synthetic resin
• CPC Class Codes: B32B 27/28 : comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
• CPC Class Codes: B32B 27/306 : comprising vinyl acetate or vinyl alcohol (co)polymers
• CPC Class Codes: B32B 27/308 : comprising acrylic (co)polymers
• CPC Class Codes: B32B 27/32 : comprising polyolefins comprising vinyl (co)polymers or acrylic (co)polymers B32B27/30
• CPC Class Codes: B32B 27/34 : comprising polyamides
• CPC Class Codes: B32B 27/36 : comprising polyesters
• CPC Class Codes: B32B 3/08 : characterised by added members at particular parts layer formed of separate pieces of material which are juxtaposed side-by-side B32B3/14, B32B3/18
• CPC Class Codes: H01G 4/005 : Electrodes
• CPC Class Codes: H01G 4/14 : Organic dielectrics
• CPC Class Codes: H01G 4/20 : using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 H01G4/12 takes precedence
• CPC Class Codes: H01G 4/206 : inorganic and synthetic material
• CPC Class Codes: H01G 4/228 : Terminals
• CPC Class Codes: H01G 4/30 : Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/33 : Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 2029/7858 : having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/26513 : of electrically active species
• CPC Class Codes: H01L 21/266 : using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 : with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 : with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 : interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 : isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 : with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 : adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 : Disposition
• CPC Class Codes: H01L 29/0869 : Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0882 : Disposition
• CPC Class Codes: H01L 29/0886 : Shape
• CPC Class Codes: H01L 29/1045 : the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/7856 : with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Claims

1. A method comprising:

forming a central well of a first conductivity type located in a substrate of the first conductivity type;

forming a doped well ring of a second conductivity type in the substrate and enclosing the central well of the first conductivity type;

forming a doped well region in the substrate adjacent the doped well ring, wherein the doped well ring is interposed between the doped well region and the central well;

forming a first doped fin contact region of the first conductivity type to form a source contact for a first fin to form a source located over the central well of the first conductivity type; and

forming a second doped fin contact region of the second conductivity type to form drain contact regions for a second fin to form a drain located over the doped well ring, wherein the drain contact regions include alternating p regions and n regions formed directly on the second fin.

2. The method of claim 1, further comprising forming a gate structure over the central well and around the first fin, wherein the gate structure is in a dielectric fill material.

3. The method of claim 2, wherein the doped well is of the first conductivity type.

4. The method of claim 3, wherein:

the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; and

the gate structure is formed partially over the deep N-well and the P-well.

5. The method of claim 4, wherein the deep N-well is formed as a ring surrounding the P-well.

6. The method of claim 3, wherein:

the first conductivity type is formed as a continuous deep N-well and the second conductivity type as a P-well; and

the gate structure is formed completely over the deep N-well.

7. The method of claim 3, wherein:

the first conductivity type is formed as a shallow N-well and the second conductivity type is a P-well;

the gate structure is formed partially over the shallow N-well and the P-well; and

the shallow N-well is formed as a ring structure.

8. The method of claim 3, wherein:

the first conductivity type is formed as a continuous shallow N-well and the second conductivity type as a P-well;

the gate structure is formed entirely over the shallow N-well; and

the first fin structure comprising the source contact is formed completely over the shallow N-well.

9. The method of claim 2, wherein the gate structure is formed over an insulating layer above the central well and is formed vertically around the first fin.

10. The method of claim 2, wherein the first doped fin contact region is formed to extend over both an upper surface of the gate structure and an upper surface of the first fin.

11. The method of claim 1, further comprising forming a shallow trench isolation (STI) structure in the doped well ring.

12. The method of claim 11, wherein a first portion of the STI structure is formed between the first fin and the second fin.

13. The method of claim 12, wherein a second portion of the STI structure is in contact with a portion of the second fin and extends over the doped well region.

14. The method of claim 13, wherein the first portion of the STI structure is formed to extend into the doped well ring and under a lower portion of the gate structure.

15. The method of claim 1, further comprising forming the first fin and the second fin using sidewall image transfer (SIT) techniques.

16. The method of claim 15, further comprising using an implantation process to form the source and the drain.