Semiconductor Device

• US 10,388,799 B2
• Filed: 02/28/2017
• Issued: 08/20/2019
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Sasaki, Toshinari
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/444,692
• Publication Number:
  US 20170170334A1
• Time in Patent Office: 903 Days
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

Claims

1. A semiconductor device comprising:

an insulating layer including a top surface and a trench, wherein the trench includes a lower end corner portion, a bottom surface, and an inner wall surface;

an oxide semiconductor film overlapping with the top surface of the insulating layer and provided in the trench, wherein the oxide semiconductor film includes a channel formation region, and wherein the channel formation region is in contact with the bottom surface, the lower end corner portion, and the inner wall surface of the trench;

a source electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a drain electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a gate insulating layer over the oxide semiconductor film; and

a gate electrode layer over the gate insulating layer,

wherein the gate insulating layer is in contact with the oxide semiconductor film in the trench, and

wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film contains indium.

3. The semiconductor device according to claim 1, wherein a carrier concentration in the oxide semiconductor film is lower than 1×

10¹⁴/cm³.

4. The semiconductor device according to claim 1, wherein a hydrogen concentration in the oxide semiconductor film is 5×

10¹⁹ atoms/cm³ or less.

5. The semiconductor device according to claim 1, wherein the bottom surface of the trench has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

20. The semiconductor device according to claim 1,

wherein the source electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the source electrode layer and the top surface of the insulating layer, and

wherein the drain electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the drain electrode layer and the top surface of the insulating layer.

6. A semiconductor device comprising:

an insulating layer including a top surface and a trench, wherein the trench includes a lower end corner portion, a bottom surface, and an inner wall surface;

an oxide semiconductor film overlapping with the top surface of the insulating layer and provided in the trench, wherein the oxide semiconductor film includes a channel formation region, and wherein the channel formation region is in contact with the bottom surface, the lower end corner portion, and the inner wall surface of the trench;

a source electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a drain electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a gate insulating layer over the oxide semiconductor film; and

a gate electrode layer over the gate insulating layer,

wherein the gate insulating layer is in contact with the oxide semiconductor film in the trench, and

wherein the insulating layer is an oxide insulating film which contains oxygen in excess of a stoichiometric composition.

7. The semiconductor device according to claim 6, wherein the insulating layer is a silicon oxide film whose composition formula is SiO_2+α

(α

>

0).

8. The semiconductor device according to claim 6, wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

9. The semiconductor device according to claim 6, wherein the oxide semiconductor film contains indium.

10. The semiconductor device according to claim 6, wherein a carrier concentration in the oxide semiconductor film is lower than 1×

10¹⁴/cm³.

11. The semiconductor device according to claim 6, wherein a hydrogen concentration in the oxide semiconductor film is 5×

10¹⁹ atoms/cm³ or less.

12. The semiconductor device according to claim 6, wherein the bottom surface of the trench has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

21. The semiconductor device according to claim 6,

wherein the source electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the source electrode layer and the top surface of the insulating layer, and

wherein the drain electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the drain electrode layer and the top surface of the insulating layer.

13. A semiconductor device comprising:

an insulating layer including a top surface and a trench, wherein the trench includes a lower end corner portion, a bottom surface, and an inner wall surface;

an oxide semiconductor film overlapping with the top surface of the insulating layer and provided in the trench, wherein the oxide semiconductor film includes a channel formation region, and wherein the channel formation region is in contact with the bottom surface, the lower end corner portion, and the inner wall surface of the trench;

a source electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a drain electrode layer over the top surface of the insulating layer and in contact with the oxide semiconductor film over the top surface of the insulating layer;

a gate insulating layer over the oxide semiconductor film; and

a gate electrode layer over the gate insulating layer,

wherein the gate insulating layer is in contact with the oxide semiconductor film in the trench, and

wherein the gate insulating layer is an oxide insulating film which contains oxygen in excess of a stoichiometric composition.

14. The semiconductor device according to claim 13, wherein the gate insulating layer is a silicon oxide film whose composition formula is SiO_2+α

(α

>

0).

15. The semiconductor device according to claim 13, wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

16. The semiconductor device according to claim 13, wherein the oxide semiconductor film contains indium.

17. The semiconductor device according to claim 13, wherein a carrier concentration in the oxide semiconductor film is lower than 1×

10¹⁴/cm³.

18. The semiconductor device according to claim 13, wherein a hydrogen concentration in the oxide semiconductor film is 5×

10¹⁹ atoms/cm³ or less.

19. The semiconductor device according to claim 13, wherein the bottom surface of the trench has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

22. The semiconductor device according to claim 13,

wherein the source electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the source electrode layer and the top surface of the insulating layer, and

wherein the drain electrode layer is provided over the top surface of the insulating layer with the oxide semiconductor film interposed between the drain electrode layer and the top surface of the insulating layer.