Trench semiconductor device having shaped gate dielectric and gate electrode structures and method

• US 10,388,801 B1
• Filed: 01/30/2018
• Issued: 08/20/2019
• Est. Priority Date: 01/30/2018
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Mudholkar, Mihir, Quddus, Mohammed T., Shin, Ikhoon, Donaldson, Scott M.
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US15/883,500
• Publication Number:
  US 20190237588A1
• Time in Patent Office: 567 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g., reduced leakage and more stable breakdown voltage) and improved reliability.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having first and second opposing major surfaces;

a trench structure comprising;

a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and

a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and

a Schottky contact region disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view, wherein;

the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;

the dielectric region comprises a first uppermost surface;

a major portion of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view; and

the first uppermost surface has a sloped shape in the cross-sectional view.

2. The semiconductor device of claim 1, wherein:

the first uppermost surface of the dielectric region extends above an upper surface of the conductive material in the cross-sectional view.

3. The semiconductor device of claim 1, wherein:

the Schottky contact region is disposed on a mesa portion of the region of semiconductor material adjacent to the trench; and

the sloped shape comprises a first portion that steps upward from an edge of the mesa portion and upwardly slopes in a direction towards the conductive material.

4. The semiconductor device of claim 1, wherein:

at least a portion of the sloped shape comprises a triangular shape.

5. The semiconductor device of claim 1, wherein:

the sloped shape comprises a trapezoid shape.

6. The semiconductor device of claim 1, wherein:

the Schottky contact region comprises a portion adjoining an upper surface of the conductive material; and

the portion adjoining the upper surface of the conductive material is disposed at least in part above the second horizontal plane in the cross-sectional view.

7. The semiconductor device of claim 1, wherein:

the sloped shape further comprises a stepped portion in the cross-sectional view.

8. The semiconductor device of claim 1, wherein:

substantially all of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view.

9. The semiconductor device of claim 1, wherein:

a major portion of the first uppermost surface is disposed above the second horizontal plane in the cross-sectional view.

10. The semiconductor device of claim 1, wherein:

the Schottky contact region is configured having an inward facing surface having a concave shape with respect to the first major surface.

11. The semiconductor device of claim 1, wherein

the Schottky contact region is configured having an inward facing surface having a convex shape with respect to the first major surface.

12. A semiconductor device comprising:

a region of semiconductor material having first and second opposing major surfaces;

a trench structure comprising;

a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and

a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and

a Schottky contact region disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view, wherein;

the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;

the dielectric region comprises a first uppermost surface;

a major portion comprising 50% or more of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view; and

the first uppermost surface comprises a stepped shape in the cross-sectional view.

13. The semiconductor device of claim 12, wherein:

a portion of the first uppermost surface further comprises a sloped shape.

14. The semiconductor device of claim 12, wherein:

the Schottky contact region comprises another portion adjoining an upper surface of the conductive material; and

the portion adjoining the upper surface of the conductive material is disposed at least in part above the second horizontal plane in the cross-sectional view.

15. The semiconductor device of claim 12, wherein:

substantially all of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view.

16. The semiconductor device of claim 12, wherein:

a major portion of the first uppermost surface is disposed above the second horizontal plane in the cross-sectional view.

17. A method of forming a semiconductor device, comprising:

providing a region of semiconductor material having first and second opposing major surfaces;

forming a trench extending into the region of semiconductor material from the first major surface;

forming a first layer of material overlying surfaces of the trench and the first major surface, the first layer of material comprising a dielectric material;

forming a second layer of material overlying the first layer of material, the second layer of material comprising a conductive material, wherein the second layer of material comprises a notch extending inward from an upper surface of the second layer of material above the trench;

removing a first portion of the second layer of material using an etch planarization step;

removing a second portion of the second layer of material using a different planarization step, wherein the step of removing the second portion of the second layer of material provides conductive material within the trench comprising a flared-out portion proximate to an upper surface of the conductive material;

removing a portion of the first layer of material to expose portions of the first major surface and to provide a dielectric region within the trench, wherein;

the dielectric region separates the conductive material from the region of semiconductor material;

the dielectric material comprises an uppermost surface; and

a major portion of the uppermost surface is disposed above a first horizontal plane defined by the exposed portions of the first major surface in a cross-sectional view; and

forming a Schottky contact region adjacent at least one of the exposed portions of the first major surface adjoining the trench.

18. The method of claim 17, wherein:

removing the first portion of the second layer of material comprises providing the second portion of the second layer of material having a thickness of approximately 0.15 microns;

removing the second portion of the second layer of material comprises using chemical mechanical planarization; and

removing the portion of the first layer of material includes providing the major portion comprising 50% or more of the uppermost surface disposed above the first horizontal plane.

19. The method of claim 17, wherein:

removing a portion of the first layer of material comprises providing the dielectric region where substantially all of the uppermost surface is disposed above the first horizontal plane; and

the method further comprises cleaning the second layer of material to remove any residual film before removing the second portion.

20. The method of claim 17, wherein:

forming the Schottky contact region comprises forming the Schottky contact region having an upper surface defining a second horizontal plane in the cross-sectional view; and

a major portion comprising 50% or more of the uppermost surface is disposed above the second horizontal plane.