Highly selective ion beam etch hard mask for sub 60nm MRAM devices

• US 10,388,862 B1
• Filed: 04/12/2018
• Issued: 08/20/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Yi, Shen, Dongna, Wang, Yu-Jen
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/951,873
• Time in Patent Office: 495 Days
• Field of Search: None
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Claims

1. A magnetic tunneling junction (MTJ) comprising:

a sub-60 nm MTJ device; and

a bottom electrode underlying said MTJ device and connected to said MTJ device by a metal via through a dielectric layer wherein said metal via has a width at least 5 nm narrower than said MTJ device wherein any metal re-deposition material lies on sidewalls of said dielectric layer and said MTJ device below a tunneling barrier layer.

2. The MTJ according to claim 1 wherein said metal via comprises Ta, Ti, TaN, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys having a width of less than 30 nm.

3. The MTJ according to claim 1 wherein said dielectric layer comprises SiO₂, SiN, SiON, SiC or SiCN.

4. The MTJ according to claim 1 further comprising:

a top electrode on said MTJ device; and

an encapsulation of said MTJ device and said top electrode with a dielectric or metal oxide comprising SiO₂, SiN, SiON, SiC, SiCN, Al₂O₃ or MgO.