3D memory device and structure
First Claim
Patent Images
1. A 3D integrated circuit device, comprising:
- a first transistor;
a second transistor; and
a third transistor,wherein said third transistor is overlaying said second transistor and is controlled by a third control line,wherein said second transistor is overlaying said first transistor and is controlled by a second control line,wherein said second transistor comprises either a mono-crystal or a polycrystalline channel,wherein said second transistor is a junction-less transistor,wherein said first transistor is part of a control circuit controlling said second control line and third control line, andwherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.
1 Assignment
0 Petitions
Accused Products
Abstract
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
-
Citations
20 Claims
-
1. A 3D integrated circuit device, comprising:
-
a first transistor; a second transistor; and a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor is a junction-less transistor, wherein said first transistor is part of a control circuit controlling said second control line and third control line, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 20)
-
-
8. A 3D integrated circuit device, comprising:
-
a first transistor; a second transistor; and a third transistor, wherein said third transistor is overlaying said second transistor and is controlled by a third control line, wherein said second transistor is overlaying said first transistor and is controlled by a second control line, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor comprises a schottky barrier, and wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A 3D integrated circuit device, comprising:
-
a first transistor; a first memory cell comprising a second transistor; and a second memory cell comprising a third transistor, wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor, wherein said first transistor is part of a control circuit controlling said first and second memory cell, wherein said second transistor comprises either a mono-crystal or a polycrystalline channel, wherein said second transistor is a junction-less transistor, wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment, and wherein said second transistor is connected to said third transistor with an ohmic connection. - View Dependent Claims (16, 17, 18, 19)
-
Specification