3D memory device and structure

• US 10,388,863 B2
• Filed: 03/07/2017
• Issued: 08/20/2019
• Est. Priority Date: 10/12/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Gurley, Lynne A
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US15/452,615
• Publication Number:
  US 20170179155A1
• Time in Patent Office: 896 Days
• Field of Search: 257 7, 257275, 257E29286, 257E21614, 257E27026
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

Claims

1. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and is controlled by a third control line,

wherein said second transistor is overlaying said first transistor and is controlled by a second control line,

wherein said second transistor comprises either a mono-crystal or a polycrystalline channel,

wherein said second transistor is a junction-less transistor,

wherein said first transistor is part of a control circuit controlling said second control line and third control line, and

wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.

2. The device according to claim 1,

wherein said second transistor is self-aligned to said third transistor.

3. The device according to claim 1,

wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.

4. The device according to claim 1,

wherein said second transistor is connected to said third transistor with an ohmic connection.

5. The device according to claim 1,

wherein at least one of said first transistors is strained for enhanced performance.

6. The device according to claim 1,

wherein said second transistor comprises a schottky barrier.

7. The device according to claim 1,

wherein said second transistor comprises a dopant segregated schottky barrier.

20. The device according to claim 1,

wherein said second transistor comprises a dopant segregated schottky barrier.

8. A 3D integrated circuit device, comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein said third transistor is overlaying said second transistor and is controlled by a third control line,

wherein said second transistor is overlaying said first transistor and is controlled by a second control line,

wherein said second transistor comprises either a mono-crystal or a polycrystalline channel,

wherein said second transistor comprises a schottky barrier, and

wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment.

9. The device according to claim 8,

wherein said second transistor is self-aligned to said third transistor.

10. The device according to claim 8,

wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell, and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.

11. The device according to claim 8,

wherein said second transistor is connected to said third transistor with an ohmic connection.

12. The device according to claim 8,

wherein said second transistor is a junction-less transistor.

13. The device according to claim 8,

wherein said first transistor is part of a control circuit controlling said second control line and third control line.

14. The device according to claim 8,

wherein said second transistor comprises a dopant segregated schottky barrier.

15. A 3D integrated circuit device, comprising:

a first transistor;

a first memory cell comprising a second transistor; and

a second memory cell comprising a third transistor,

wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,

wherein said first transistor is part of a control circuit controlling said first and second memory cell,

wherein said second transistor comprises either a mono-crystal or a polycrystalline channel,

wherein said second transistor is a junction-less transistor,

wherein said first transistor, said second transistor and said third transistor are all aligned to each other with less than 100 nm misalignment, and

wherein said second transistor is connected to said third transistor with an ohmic connection.

16. The device according to claim 15,

wherein said second transistor is self-aligned to said third transistor.

17. The device according to claim 15,

wherein said third transistor is a part of a third memory cell, said second transistor is a part of a second memory cell and said first transistor is a part of memory periphery circuits controlling said third and second memory cells.

18. The device according to claim 15,

wherein said second transistor is a junction-less transistor.

19. The device according to claim 15,

wherein said second transistor comprises a schottky barrier.