Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor

• US 10,389,356 B2
• Filed: 04/25/2018
• Issued: 08/20/2019
• Est. Priority Date: 05/17/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Joshi, Rajiv V., Wang, Naigang
• Primary Examiner(s): Kim, Seokjin
• Application Number:
  US15/962,510
• Publication Number:
  US 20180337679A1
• Time in Patent Office: 482 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/017509 Interface arrangements

Abstract

A circuit and method are provided. The circuit and method are for providing a supply voltage. The circuit includes a first transistor and a second transistor, coupled to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

Claims

1. A circuit for providing a supply voltage, comprising:

a first transistor and a second transistor, of different channel types from among N and P channel types, coupled to a static power supply that supplies a constant power supply voltage, the second transistor having two gate terminals connected to a gate terminal of the first transistor; and

a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to a dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

2. The circuit of claim 1, further comprising a capacitor, different from the at least one capacitance, connected in parallel to the magnetic inductor such that a first terminal of the capacitor is connected to the common node between the first transistor and the second transistor and a second terminal of the capacitor is connected to the dynamic internal power supply node.

3. The circuit of claim 1, wherein the first transistor is disabled in response to a first phase of a boost clock that is synchronized with a functional clock of the group of other circuits that controls an evaluation for dynamic logic circuits and state changes for static logic circuits in the group of other circuits.

4. The circuit of claim 3, wherein the magnetic inductor resonates with the at least one capacitance to supply the dynamic internal power supply node with the boosted voltage, responsive to the first transistor being disabled during a second phase of the boost clock.

5. The circuit of claim 4, wherein the second phase of the boost clock is provided at a timing corresponding to the evaluation time for the dynamic logic circuits and the state changes for the static logic circuits to provide the boost voltage during the evaluation time and the state changes.

6. The circuit of claim 1, wherein the second transistor has the two gates terminal coupled to a boost clock, a source terminal connected to the dynamic internal power supply node, and a drain terminal connected to the static power supply.

7. The circuit of claim 6, wherein the first transistor has a source terminal connected to the source terminal of the second transistor, and a drain terminal connected the drain terminal of the second transistor.

8. The circuit of claim 1, whereby the second transistor is enabled by a first phase of a boost clock and has a source terminal connected to a source terminal of the first transistor, whereby the first transistor and the second transistor couple the magnetic inductor and the at least one capacitance to the static power supply.

9. The circuit of claim 1, wherein the group of other circuits are connected between the dynamic internal power supply node and a return node, and wherein the at least one capacitance includes a shunt capacitance resulting from the group of other circuits.

10. The circuit of claim 1, wherein the other circuits are selected from the group consisting of logic circuits, memory circuits, and circuits having both logic and memory elements.

11. A method for forming an integrated circuit providing a supply voltage, comprising:

forming a first transistor and a second transistor, of different channel types from among N and P channel types, coupled to a static power supply that supplies a constant power supply voltage, the second transistor having two gate terminals connected to a gate terminal of the first transistor; and

forming an on-chip magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to a dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

12. The method of claim 11, further comprising forming a capacitor, different from the at least one capacitance, connected in parallel to the magnetic inductor such that a first terminal of the capacitor is connected to the common node between the first transistor and the second transistor and a second terminal of the capacitor is connected to the dynamic internal power supply node.

13. The method of claim 11, further comprising disabling the first transistor in response to a first phase of a boost clock that is synchronized with a functional clock of the group of other circuits that controls an evaluation for dynamic logic circuits and state changes for static logic circuits in the group of other circuits.

14. The method of claim 13, wherein the magnetic inductor is formed to resonate with the at least one capacitance to supply the dynamic internal power supply node with the boosted voltage, responsive to the first transistor being disabled during a second phase of the boost clock.

15. The method of claim 14, further comprising providing the second phase of the boost clock at a timing corresponding to the evaluation time for the dynamic logic circuits and the state changes for the static logic circuits to provide the boost voltage during the evaluation time and the state changes.

16. The method of claim 11, further comprising:

coupling the two gate terminals of the second transistor to a boost clock;

connecting a source terminal of the second transistor to the dynamic internal power supply node; and

connecting a drain terminal of the second transistor to the static power supply.

17. The method of claim 16, further comprising coupling a source terminal of the first transistor to the source terminal of the second transistor, and a drain terminal of the first transistor to the drain terminal of the second transistor.

18. The method of claim 11, whereby the second transistor is enabled by a first phase of a boost clock and has a source terminal connected to a source terminal of the first transistor, whereby the first transistor and the second transistor couple the magnetic inductor and the at least one capacitance to the static power supply.

19. The method of claim 11, wherein the group of other circuits are connected between the dynamic internal power supply node and a return node, and wherein the at least one capacitance includes a shunt capacitance resulting from the group of other circuits.

20. The method of claim 11, wherein the other circuits are selected from the group consisting of logic circuits, memory circuits, and circuits having both logic and memory elements.