Secure data storage

• US 10,389,522 B2
• Filed: 02/04/2017
• Issued: 08/20/2019
• Est. Priority Date: 02/05/2016
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Riou, Sebastien
• Primary Examiner(s): Colin, Carl G
• Assistant Examiner(s): Lavelle, Gary E
• Application Number:
  US15/424,842
• Publication Number:
  US 20170230169A1
• Time in Patent Office: 927 Days
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07309 Means for preventing undesired reading or writing from or onto record carriers
• CPC Class Codes: G06K 19/07318 by hindering electromagnetic reading or writing jamming of communication, counter-measures H04K3/00; secret communication H04K1/00
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/004 for fault attacks
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

The disclosure relates to secure data storage and retrieval, in particular to methods and circuits for securely storing data to reduce the possibility of leakage via side channel attacks. Embodiments disclosed include a method of storing a value comprising a series of words, the method comprising: i) combining in a series of XOR operations a word of a first portion of the value, a word of a second portion of the value and an output word of a first random number generator to provide a first combined word; ii) storing the first combined word in a shift register; and iii) repeating steps i) and ii) for each successive word of the first and second portions of the value.

Claims

1. A method of securely storing a value comprising a series of words, the method comprising:

i) combining, with a first XOR gate, a word of a first portion of the value, and an output word of a first pseudo random number generator, and combining, with a second XOR gate, output of the first XOR gate with a word of a second portion of the value, to provide a first combined word;

ii) storing the first combined word in a shift register;

iii) repeating steps i) and ii) for each successive word of the first and second portions of the value;

iv) outputting a first output word from the shift register;

combining, with a third XOR gate, the first output word with an output word of a true random number generator to provide a first combined output word;

v) outputting a second output word from a second pseudo random number generator; and

combining, with a fourth XOR gate, the second output word with the output word of the true random number generator to provide a second combined output word; and

vi) repeating steps iv) and v) for each successive word stored in the shift register.

2. The method of claim 1, wherein the first pseudo random number generator and the second pseudo random number generator are configured to generate the same sequence of words, and the outputs from the first pseudo random number generator and the second pseudo random number generator are shifted relative to each other in the sequence of words by a length of the shift register.

3. The method of claim 1, wherein step i) further comprises:

ia) combining, with the third XOR gate, the output word of the first pseudo random number generator with an output word of the true random number generator to provide a second combined word;

ib) combining, with the fourth XOR gate, the word of the second portion of the value with the second combined word to provide a third combined word;

ic) combining, with a fifth XOR gate, the output word of the true random number generator with the word of the first portion of the value to provide a fourth combined word; and

id) combining, with a sixth XOR gate, the fourth combined word with the third combined word to provide the first combined word.

4. The method of claim 1, wherein the true random number generator generates a different sequence of words to the sequence of words generated by the first and second pseudo random number generators.

5. A circuit for storing a value comprising a series of words, the circuit comprising:

a first input configured to receive a word of a first portion of the value;

a second input configured to receive a word of a second portion of the value;

a first pseudo random number generator;

a second pseudo random number generator;

a true random number generator;

a first XOR gate having inputs connected to the second input and an output of the first pseudo random number generator;

a second XOR gate having inputs connected to the first input and an output of the first XOR gate;

a shift register having an input connected to an output of the second XOR gate and having an output;

a third XOR gate connected between the first input and the second XOR gate, the third XOR gate having inputs connected to the first input and an output of the true random number generator and an output connected to an input of the second XOR gate; and

a fourth XOR gate connected between the first pseudo random number generator and the first XOR gate, the fourth XOR gate having inputs connected to the first pseudo random number generator and the true random number generator and an output connected to an input of the first XOR gate.

6. The circuit of claim 5, wherein the first pseudo random number generator and the pseudo second random number generator are configured to generate the same sequence of words, and the outputs from the first pseudo random number generator and the second pseudo random number generator are shifted relative to each other in the sequence of words by a length of the shift register.

7. The circuit of claim 6, wherein the true random number generator is configured to generate a different sequence of words to the sequence of words generated by the first and second pseudo random number generators.

8. The circuit of claim 5, further comprising:

a fifth XOR gate having inputs connected to the output of the shift register and the true random number generator; and

a sixth XOR gate having inputs connected to the second random number generator and the true random number generator.

9. A card comprising an integrated circuit (IC) having the circuit according to claim 5.