Gate boosting circuit and method for an integrated power stage

• US 10,394,260 B2
• Filed: 06/26/2017
• Issued: 08/27/2019
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Shen, Dan, Crespi, Lorenzo
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/633,527
• Publication Number:
  US 20180004238A1
• Time in Patent Office: 792 Days
• Field of Search: 327109
• CPC Class Codes: G05F 1/462 as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

Systems and methods according to one or more embodiments are provided for gate boosted drivers for integrated power stages. In one example, a gate driver includes an output stage comprising an n-channel metal-oxide-semiconductor (NMOS) pull-up transistor and an NMOS pull-down transistor, where the NMOS pull-up transistor and the NMOS pull-down transistor are coupled at an output node. The gate driver further includes a bootstrap circuit comprising a main bootstrap capacitor, where the bootstrap capacitor provides a supply voltage for driving the NMOS pull-up transistor. The gate driver further includes a high voltage generator coupled with the main bootstrap capacitor via a transistor switch and a replica bootstrap circuit comprising a replica bootstrap capacitor. The replica bootstrap circuit generates a reference voltage that regulates a drain current of the transistor switch, and the regulated drain current of the transistor switch charges the main bootstrap capacitor from the high voltage generator.

Claims

1. A gate driver comprising:

an output stage comprising an n-channel metal-oxide-semiconductor (NMOS) pull-up transistor and an NMOS pull-down transistor, wherein the NMOS pull-up transistor and the NMOS pull-down transistor are coupled at an output node;

a bootstrap circuit comprising a main bootstrap capacitor, wherein the bootstrap capacitor provides a supply voltage for driving the NMOS pull-up transistor;

a high voltage generator coupled with the main bootstrap capacitor via a transistor switch; and

a replica bootstrap circuit comprising a replica bootstrap capacitor, wherein the replica bootstrap capacitor generates a reference voltage that regulates a drain current of the transistor switch, and wherein the regulated drain current of the transistor switch charges the main bootstrap capacitor from the high voltage generator;

wherein the replica bootstrap circuit further comprises a first voltage source and a first diode, the first voltage source configured to charge the replica bootstrap capacitor via the first diode when the first diode is forward biased.

2. The gate driver of claim 1, wherein the reference voltage is substantially the same as a voltage generated by combining a voltage at the output node, a maximum allowed gate overdrive voltage, and a threshold voltage of the transistor switch.

3. The gate driver of claim 1, further comprising a second voltage source and a second diode, wherein the second voltage source charges the main bootstrap capacitor via the second diode when the second diode is forward biased.

4. The gate driver of claim 3, wherein a voltage provided by the second voltage source is less than or equal to the voltage provided by the first voltage source.

5. The gate driver of claim 1, further comprising a level shifter circuit configured to translate a voltage level of an input signal, wherein an output of the level shifter circuit is coupled to a gate of the NMOS pull-up transistor.

6. The gate driver of claim 1, further comprising a charge pump module, wherein the charge pump module charges a gate capacitance of the NMOS pull-up transistor and the main bootstrap capacitor when the transistor switch is conducting current.

7. The gate driver of claim 1, wherein the NMOS pull-up transistor occupies a larger die area than the transistor switch.

8. The gate driver of claim 1, wherein the replica bootstrap capacitor exhibits a substantially small capacitance.

9. The gate driver of claim 1, wherein the transistor switch conducts the drain current when a voltage across the main bootstrap capacitor is below the reference voltage by a threshold voltage of the transistor switch.

10. The gate driver of claim 1, wherein the transistor switch is an NMOS transistor switch.

11. A method for operating a gate driver for an integrated power stage comprising:

charging a main bootstrap capacitor;

charging a replica bootstrap capacitor from a first voltage source via a first diode when the first diode is forward biased;

providing a supply voltage for driving a pull-up n-channel metal-oxide-semiconductor (NMOS) transistor from the main bootstrap capacitor;

providing a reference voltage at a gate terminal of a transistor switch, wherein the reference voltage regulates a drain current of the transistor switch and wherein the regulated drain current of the transistor switch charges the main bootstrap capacitor from a high voltage generator; and

conducting the drain current through the transistor switch when a voltage across the bootstrap capacitor is below the reference voltage by a threshold voltage of the transistor switch;

wherein the replica bootstrap capacitor generates a reference voltage that regulates a drain current of the transistor switch.

12. The method of claim 11, wherein the reference voltage is substantially same as a voltage obtained by combining a voltage at an output node, a maximum allowed gate overdrive voltage, and the threshold voltage of the transistor switch.

13. The method of claim 11, wherein the main bootstrap capacitor is charged from a second voltage source via a second diode when the second diode is forward biased.

14. The method of claim 13, further comprising blocking a current flow from the main bootstrap capacitor to the second voltage source via the second diode, wherein the second diode is reverse biased during the blocking.

15. The method of claim 11, further comprising blocking a current flow from the replica bootstrap capacitor to the first voltage source via the second first diode, wherein the first diode is reverse biased during the blocking.

16. The method of claim 11, wherein the transistor switch conducts the drain current when a voltage across the main bootstrap capacitor is below the reference voltage by the threshold voltage of the transistor switch.

17. The method of claim 11, wherein the transistor switch is an NMOS transistor switch.