System and method for reducing display artifacts

• US 10,394,391 B2
• Filed: 06/30/2015
• Issued: 08/27/2019
• Est. Priority Date: 01/05/2015
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Reynolds, Joseph Kurth, Morein, Stephen L., Shamarao, Prashant
• Primary Examiner(s): Patel, Nitin
• Assistant Examiner(s): Stone, Robert M
• Application Number:
  US14/788,660
• Publication Number:
  US 20160195957A1
• Time in Patent Office: 1,519 Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer

Abstract

In an example, a processing system for an integrated display device and capacitive sensing device includes driver circuitry and a driver module. The driver circuitry is configured for coupling to a plurality of source lines and a plurality of sensor electrodes, where each of the plurality of sensor electrodes comprises at least one common electrode configured for display updating and capacitive sensing. The driver module is coupled to the driver circuitry and configured to drive the plurality of sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, where the non-display update period is at least as long as one of the first and second display line update periods. The driver module is further configured to operate each of the plurality of source lines to reduce display artifacts during the non-display update period.

Claims

1. A processing system for an integrated display device and capacitive sensing device, comprising:

driver circuitry configured for coupling to a plurality of source lines and a plurality of sensor electrodes, each of the plurality of sensor electrodes comprising at least one common electrode configured for display updating and capacitive sensing; and

a driver module coupled to the driver circuitry and configured to;

drive the plurality of sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, and during a second non-display update period that occurs between the second and a third display line update periods of the display frame, where each of the first and the second non-display update periods is at least as long as one of the first, second, and third display line update periods;

hold a first source line of the plurality of source lines at a first source voltage during a full length of the first non-display update period;

hold a second source line of the plurality of source lines at a second source voltage during the full length of the first non-display update period;

hold the first source line at a third source voltage during a full length of the second non-display update period; and

hold the second source line at a fourth source voltage during the full length of the second non-display update period, wherein each of the first source voltage, the second source voltage, the third source voltage and the fourth source voltage are different.

2. The processing system of claim 1, wherein the capacitive sensing comprises absolute capacitive sensing.

3. The processing system of claim 1, wherein the capacitive sensing comprises transcapacitive sensing.

4. The processing system of claim 1, wherein the first source voltage corresponds to the second display line update period and the third source voltage corresponds to the third display line update period.

5. The processing system of claim 1, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period;

the first source voltage and the second source voltage correspond to the first display line update period; and

the first gate line is re-selected in the second display line update period.

6. The processing system of claim 1, wherein the driver module is configured to operate each of the plurality of source lines to reduce display artifacts during the first non-display update period by either driving the plurality of source lines with a constant voltage or electrically floating the plurality of source lines.

7. The processing system of claim 6, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period; and

the driver module is configured to operate each of the plurality of source lines to reduce display artifacts during the first non-display update period by re-selecting the first gate line in the second display line update period.

8. The processing system of claim 7, wherein the duration of the second display line update period is longer than the first display line update period.

9. The processing system of claim 6, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period and a second gate line of the plurality of gate lines is selected during the second display line update period; and

the driver module is configured to operate each of the plurality of source lines to reduce display artifacts during the first non-display update period by re-selecting the second gate line in a third display line update period after the second display line update period.

10. The processing system of claim 6, wherein the duration of the second display line update period is longer than the first display line update period.

11. The processing system of claim 1, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period and a second gate line of the plurality of gate lines is selected during the second display line update period;

the first source voltage and the second source voltage correspond to the first display line update period; and

the second gate line is re-selected in the third display line update period.

12. The processing system of claim 1, wherein:

the first source voltage and the second source voltage correspond to the first display line update period; and

wherein the duration of the second display line update period is longer than the first display line update period.

13. An integrated display device and capacitive sensing device, comprising:

a plurality of source lines;

a plurality of sensor electrodes, each of the plurality of sensor electrodes comprising at least one common electrode configured for display updating and capacitive sensing; and

a processing system, coupled to the plurality of source lines and the plurality of sensor electrodes, the processing system configured to;

drive the plurality of sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, and during a second non-display update period that occurs between the second and third display line update periods of the display frame, where each of the first and the second non-display update periods is at least as long as one of the first, second, and third display line update periods;

hold a first source line of the plurality of source lines at a first source voltage during a full length of the first non-display update period;

hold a second source line of the plurality of source lines at a second source voltage during the full length of the first non-display update period;

hold the first source line at a third source voltage during a full length of the second non-display update period; and

hold the second source line at a fourth source voltage during the full length of the second non-display update period, wherein each of the first source voltage, the second source voltage, the third source voltage, and the fourth source voltage are different.

14. The device of claim 13, wherein the first source voltage corresponds to the second display line update period and the third source voltage corresponds to the third display line update period.

15. The device of claim 13, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period;

the first source voltage and the second source voltage correspond to the first display line update period; and

the first gate line is re-selected in the second display line update period.

16. The device of claim 13, wherein the processing system is configured to operate each of the plurality of source lines to reduce display artifacts during the first non-display update period by either driving the plurality of source lines with a constant voltage or electrically floating the plurality of source lines.

17. A method of operating an integrated display device and capacitive sensing device having a plurality of source lines and a plurality of sensor electrodes, the plurality of sensor electrodes disposed in a matrix array on a common electrode layer for display updating and capacitive sensing, the method comprising:

driving the plurality of sensor electrodes for absolute capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, and during a second non-display update period that occurs between the second and a third display line update periods of the display frame, where each of the first and the second non-display update periods is at least as long as one of the first, second, and third display line update periods;

holding a first source line of the plurality of source lines at a first source voltage during a full length of the first non-display update period;

holding a second source line of the plurality of source lines at a second source voltage during the full length of the first non-display update period;

holding the first source line at a third source voltage during a full length of the second non-display update period; and

holding the second source line at a fourth source voltage during the full length of the second non-display update period, wherein each of the first source voltage, the second source voltage, the third source voltage, and the fourth source voltage are different.

18. The method of claim 17, wherein the first source voltage corresponds to the second display line update period and the third source voltage corresponds to the third display line update period.

19. The method of claim 17, wherein:

a first gate line of a plurality of gate lines is selected during the first display line update period;

the first source voltage and the second source voltage correspond to the first display line update; and

the first gate line is reselected in the second display line update period.

20. The method of claim 17, wherein the step of operating comprises either driving the plurality of source lines with a constant voltage or electrically floating the plurality of source lines.

21. An integrated display device and capacitive sensing device, comprising:

a plurality of source lines;

a matrix array of sensor electrodes disposed on a common electrode layer for display updating and capacitive sensing; and

a processing system, coupled to the plurality of source lines and the sensor electrodes, the processing system configured to;

drive the sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, and during a second non-display update period that occurs between the second and a third display line update periods of the display frame, where each of the first and the second non-display update periods is at least as long as one of the first, second, and third display line update periods; and

hold a first source line of the plurality of source lines at a first source voltage during a full length of the first non-display update period;

hold a second source line of the plurality of source lines at a second source voltage during the full length of the first non-display update period;

hold the first source line at a third source voltage during a full length of the second non-display update period; and

hold the second source line at a fourth source voltage during the full length of the second non-display update period, wherein each of the first source voltage, the second source voltage, the third source voltage, and the fourth source voltage are different.