True random number generator and oscillator

• US 10,394,526 B2
• Filed: 10/30/2017
• Issued: 08/27/2019
• Est. Priority Date: 11/09/2016
• Status: Active Grant

• Current Assignee: Postech Academy-Industry Foundation
• Original Assignee: Postech Academy-Industry Foundation
• Inventors: Kim, Eunhwan, Kim, Jae-Joon
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US15/798,267
• Publication Number:
  US 20180129477A1
• Time in Patent Office: Days
• Field of Search: 708251
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes

Abstract

Provided are a true random number generator and an oscillator. The random number generator includes an oscillator configured to output signals and oscillate a random number of times until phases of the signals being output are inverted with respect to each other after initialization, and a counter configured to count the number of oscillations. The counted number of oscillations is used as a seed for generating a random number.

Claims

1. A random number generator comprising:

an oscillator configured to output signals which oscillate a random number of times due to noise after initialization;

a phase detector configured to receive the output signals and determine whether phases of the output signals have been inverted with respect to each other; and

a counter configured to count the number of oscillations of the output signals until the phases of the output signals are inverted with respect to each other,

wherein the counted number of oscillations is used as a seed for generating a random number.

2. The random number generator of claim 1, wherein when the phases of the output signals are inverted with respect to each other, a phase difference between the output signals is 180 degrees.

3. The random number generator of claim 2, further comprising:

a switch configured to provide the output signals of the oscillator to the counter or block the output signals,

wherein the switch is controlled to be turned on or off by an output of the phase detector.

4. The random number generator of claim 1, wherein the output signals are in phase at the initialization.

5. The random number generator of claim 1, further comprising:

a post processing unit including a register configured to store the number of oscillations counted by the counter, and a calculator configured to perform a logical operation on the number of oscillations.

6. The random number generator of claim 5, wherein the register stores the number of oscillations as binary information, and

the calculator performs an exclusive disjunction operation (exclusive OR) on bits to generate a random number.

7. The random number generator of claim 1, further comprising:

a pulse generator configured to initialize the oscillator by providing an initialization signal.

8. The random number generator of claim 7, wherein the initialization signal is provided to the counter to initialize the counter.

9. An oscillator for generating a random number, wherein unit cells are cascaded to oscillate and individually include a pair of output circuits, and each of the pair of output circuits includes:

a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor connected between a driving voltage and a common node and having gate electrodes connected to each other to receive an input signal, wherein the common nodes of the pair of output circuits are connected to form a single node; and

input signal degrading resistances connected between a drain electrode of the PMOS transistor and a drain electrode of the NMOS transistor and configured to reduce influence of the input signal on an output signal and increase influence of noise.

10. The oscillator of claim 9, wherein the input signal degrading resistances connected between the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor include:

a first input signal degrading resistance connected between the drain electrode of the PMOS transistor and an output node; and

a second input signal degrading resistance connected between the drain electrode of the NMOS transistor and the output node.

11. The oscillator of claim 9, wherein each of the pair of output circuits further includes:

a feedback resistance connected between an input node to which the input signal is provided and an output node from which the output signal is provided.

12. The oscillator of claim 9, wherein each of the unit cells further includes:

reset transistors configured to reset the pair of output circuits.

13. The oscillator of claim 9, wherein each of the unit cells further includes:

an activation transistor connected to the common node and configured to activate the unit cell.