Adaptive bug-search depth for simple and deep counterexamples

• US 10,394,987 B2
• Filed: 03/21/2017
• Issued: 08/27/2019
• Est. Priority Date: 03/21/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Baumgartner, Jason R., Gajavelly, Raj K., Mony, Hari, Nalla, Pradeep K.
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US15/464,808
• Publication Number:
  US 20180276317A1
• Time in Patent Office: Days
• Field of Search: 716111
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Claims

1. A computer system comprising:

a processor in communication with one or more types of memory, the processor configured to;

provide a netlist indicative of connectivity and functional states of components of an integrated circuit design;

iteratively search through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations, wherein iteratively searching through the netlist at a selected depth to locate errors within the netlist comprises performing a simulation process and a symbolic analysis process;

adaptively adjust the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations;

adaptively adjust an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations; and

manufacture the integrated circuit design.

2. The computer system of claim 1 wherein the selected depth of the netlist comprises a number of simulation cycles by which the processor is configured to iteratively search.

3. The computer system of claim 1 wherein an amount of coverage of the netlist is determined by at least one of analysis of the functional states of the components of the integrated circuit design and of analysis of secondary properties of the components of the integrated circuit design.

4. The computer system of claim 1 wherein the processor is further configured to determine a depth of the netlist depending on a length of a trace associated with a gate component of the integrated circuit design, and to shorten the length of the trace, wherein the trace comprises a sequence of valuations of the gate component of the integrated circuit design.

5. The computer system of claim 4 wherein the processor is further configured to shorten the length of the trace starting from a first state of the gate component that is later in time than a second state of the gate component.

6. The computer system of claim 1 wherein the processor is located in a cloud computing environment, and wherein the program instructions are implemented in software run by the processor located in the cloud computing environment.

7. A computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method of designing an integrated circuit comprising;

providing a netlist indicative of connectivity and functional states of components of the integrated circuit design;

iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations, wherein iteratively searching through the netlist at a selected depth to locate errors within the netlist comprises performing a simulation process and a symbolic analysis process;

adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations;

adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations; and

manufacturing the integrated circuit design.

8. The computer program product of claim 7 wherein the selected depth of the netlist comprises a number of simulation cycles by which iteratively searching by the processing circuit is performed.

9. The computer program product of claim 7 wherein an amount of coverage of the netlist is determined by at least one of analysis of the functional states of the components of the integrated circuit design and of analysis of secondary properties of the components of the integrated circuit design.

10. The computer program product of claim 7 further comprising determining a depth of the netlist depending on a length of a trace associated with a gate component of the integrated circuit design, and shortening the length of the trace, wherein the trace comprises a sequence of valuations of the gate component of the integrated circuit design.

11. The computer program product of claim 10 further comprising shortening the length of the trace starting from a first state of the gate component that is later in time than a second state of the gate component.