Display device

• US 10,395,593 B2
• Filed: 01/12/2018
• Issued: 08/27/2019
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Toyotaka, Kouhei
• Primary Examiner(s): Sitta, Grant
• Application Number:
  US15/869,724
• Publication Number:
  US 20180137822A1
• Time in Patent Office: 592 Days
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.

Claims

1. A display device comprising:

a driver circuit comprising a first circuit, a second circuit, and first to fourth transistors;

a pixel comprising an EL element and fifth to seventh transistors; and

a gate line,

wherein the first circuit is configured to output a first signal to the second circuit,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein the first wiring is configured to output a first clock signal,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein a potential of the gate of the second transistor is controlled in accordance with the first signal,

wherein the fifth transistor is configured to supply current to the EL element,

wherein the sixth transistor is configured to control input of an image signal to the pixel,

wherein the fifth transistor and the seventh transistor are electrically connected to each other in series between a power supply line and the EL element, and

wherein the gate line is electrically connected to the one of the source and the drain of the third transistor, and the gate line is directly connected to a gate of the seventh transistor.

2. The display device according to claim 1,

wherein the first circuit comprises an eighth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to a second wiring,

wherein the second wiring is configured to supply a second clock signal, and

wherein the first signal is output through the eighth transistor in accordance with the second clock signal.

3. The display device according to claim 1,

wherein the second circuit is configured to output a second signal, and

wherein the second signal is delayed compared to the first signal.

4. A display device comprising:

a driver circuit comprising a first circuit, a second circuit, and first to fourth transistors;

a pixel comprising an EL element and fifth to seventh transistors; and

a gate line,

wherein the first circuit is configured to output a first signal to the second circuit,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein the first wiring is configured to output a first clock signal,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein a potential of the gate of the second transistor is controlled in accordance with the first signal,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein the fifth transistor is configured to supply current to the EL element,

wherein the sixth transistor is configured to control input of an image signal to the pixel,

wherein the fifth transistor and the seventh transistor are electrically connected to each other in series between a power supply line and the EL element, and

wherein the gate line is electrically connected to the one of the source and the drain of the third transistor, and the gate line is directly connected to a gate of the seventh transistor.

5. The display device according to claim 4,

wherein the first circuit comprises an eighth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to a second wiring,

wherein the second wiring is configured to supply a second clock signal, and

wherein the first signal is output through the eighth transistor in accordance with the second clock signal.

6. The display device according to claim 4,

wherein the second circuit is configured to output a second signal, and

wherein the second signal is delayed compared to the first signal.

7. A display device comprising:

a driver circuit comprising a first circuit, a second circuit, and first to fourth transistors;

a pixel comprising an EL element and fifth to seventh transistors; and

a gate line,

wherein the first circuit is configured to output a first signal to the second circuit,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein the first wiring is configured to output a first clock signal,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein a potential of the gate of the second transistor is controlled in accordance with the first signal,

wherein a first potential is supplied to the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor,

wherein a second potential is supplied to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor,

wherein the fifth transistor is configured to supply current to the EL element,

wherein the sixth transistor is configured to control input of an image signal to the pixel,

wherein the fifth transistor and the seventh transistor are electrically connected to each other in series between a power supply line and the EL element, and

wherein the gate line is electrically connected to the one of the source and the drain of the third transistor, and the gate line is directly connected to a gate of the seventh transistor.

8. The display device according to claim 7,

wherein the first circuit comprises an eighth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to a second wiring,

wherein the second wiring is configured to supply a second clock signal, and

wherein the first signal is output through the eighth transistor in accordance with the second clock signal.

9. The display device according to claim 7,

wherein the second circuit is configured to output a second signal, and

wherein the second signal is delayed compared to the first signal.