Driver circuit

• US 10,395,612 B2
• Filed: 12/01/2016
• Issued: 08/27/2019
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Huang, Sheng-Feng, Iwatsu, Akihiro, Wu, Cheng-Min, Lee, Kuanfeng
• Primary Examiner(s): Rosario, Nelson M
• Assistant Examiner(s): Lee, Andrew
• Application Number:
  US15/365,990
• Publication Number:
  US 20170162145A1
• Time in Patent Office: 999 Days
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Claims

1. A driver circuit, comprising:

an output circuit comprising a pull-up transistor, and the pull-up transistor comprising a silicon semiconductor layer; and

a control circuit coupled to the output circuit, the control circuit comprising a first transistor, and the first transistor comprising an oxide semiconductor layer;

wherein the pull-up transistor has a first control node, and the pull-up transistor is coupled to a first clock signal and a gate line;

wherein the output circuit further comprises an auxiliary transistor coupled to the pull-up transistor and a low voltage, and the auxiliary transistor has a second control node;

wherein the control circuit further comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

wherein the pull-up transistor is further coupled to the seventh transistor;

wherein the auxiliary transistor is further coupled to the second transistor, the third transistor and the fourth transistor;

wherein the first transistor is coupled to the high voltage;

wherein the second transistor is coupled to the low voltage, the first control node, the first transistor and the seventh transistor;

wherein the third transistor is coupled to a second control signal and the high voltage;

wherein the fourth transistor is coupled to the low voltage, the first transistor, the fifth transistor and the sixth transistor;

wherein the fifth transistor is coupled to a third control signal and a previous gate line;

wherein the sixth transistor is coupled to a fourth control signal and a next gate line;

wherein each of the pull-up transistor, the auxiliary transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor has a first end, a second end and a third end.

2. The driver circuit as claimed in claim 1, wherein the first end of the pull-up transistor is connected to the first clock signal;

the second end of the pull-up transistor is connected to the gate line and the first end of the auxiliary transistor;

the third end of the pull-up transistor is connected to the first end of the seventh transistor;

wherein the second end of the auxiliary transistor is connected to the low voltage; and

the third end of the auxiliary transistor is connected to the second control node, the second end of the third transistor, the third end of the second transistor and the first end of the fourth transistor;

wherein the first end of the third transistor is connected to the high voltage, and the third end of the third transistor is connected to the second control signal;

wherein the second end of the fourth transistor is connected to the low voltage;

the third end of the fourth transistor is connected to the second end of the fifth transistor, the second end of the sixth transistor and the third end of the first transistor;

wherein the first end of the fifth transistor is connected to the previous gate line; and

the third end of the fifth transistor is connected to the third control signal;

wherein the first end of the sixth transistor is connected to the next gate line, and the third end of the sixth transistor is connected to the fourth control signal.

3. The driver circuit as claimed in claim 1, wherein at least one of the second transistor and the fourth transistor comprises an oxide semiconductor layer.

4. The driver circuit as claimed in claim 1, wherein the control circuit further comprises a capacitor between the second end and the third end of the pull-up transistor.

5. The driver circuit as claimed in claim 1, wherein the first end of the seventh transistor is connected to the third end of the pull-up transistor, the second end of the seventh transistor is connected to the second end of the first transistor, and the third end of the seventh transistor is connected to the high voltage.

6. The driver circuit as claimed in claim 1, wherein the control circuit further comprises an eighth transistor having a first end connected to the third end of the auxiliary transistor, a second end connected to the low voltage, and a third end connected to the second end of the pull-up transistor.

7. The driver circuit as claimed in claim 1, wherein the control circuit further comprises a ninth transistor having a first end connected to a reset signal, a second end connected to the third end of the auxiliary transistor, and a third end connected to the reset signal.

8. The driver circuit as claimed in claim 1, wherein the second transistor and the sixth transistor have a stack-up structure of a commonly-shared gate.

9. A driver circuit, comprising:

an output circuit comprising a pull-up transistor, and the pull-up transistor comprising a silicon semiconductor layer; and

a control circuit coupled to the output circuit, the control circuit comprising a first transistor, and the first transistor comprising an oxide semiconductor layer;

wherein the pull-up transistor has a first control node, and the pull-up transistor is coupled to a first clock signal and a gate line;

wherein the output circuit further comprises an auxiliary transistor coupled to the pull-up transistor and a low voltage, and the auxiliary transistor has a second control node;

wherein the control circuit further comprises a second transistor, a third transistor, and a fourth transistor;

wherein the first transistor is coupled to the first control node;

wherein the second transistor is coupled to the first control node, the low voltage, and the second control node;

wherein the third transistor is coupled to a high voltage and the second control node;

wherein the fourth transistor is coupled to the second control node and the low voltage;

wherein at least one of the second transistor, the third transistor and the fourth transistor comprises an oxide semiconductor layer;

wherein the control circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

wherein the pull-up transistor is further coupled to the first transistor,

wherein the auxiliary transistor is further coupled to the third transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor;

wherein the first transistor is coupled to the high voltage;

wherein the third transistor is coupled to the high voltage, the eighth transistor and the tenth transistor;

wherein the fourth transistor is coupled to the low voltage, the first control node, the first transistor, the second transistor, the seventh transistor and the ninth transistor;

wherein the sixth transistor is coupled to the low voltage, the fifth transistor and a first control signal line;

wherein the seventh transistor is coupled to a first input signal line, a second control signal line and the eighth transistor;

wherein the ninth transistor is coupled to a second input signal, a third control signal and the tenth transistor, the eighth transistor being coupled to a fourth control signal; and

wherein the tenth transistor is coupled to a fifth control signal;

wherein each of the pull-up transistor, the auxiliary transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor has a first end, a second end and a third end.

10. The driver circuit as claimed in claim 9, wherein the first end of the pull-up transistor is connected to the first clock signal;

the second end of the pull-up transistor is connected to the gate line and the first end of the auxiliary transistor; and

the third end of the pull-up transistor is connected to the first end of the first transistor;

wherein the second end of the auxiliary transistor is connected to the low voltage;

the third end of the auxiliary transistor is connected to the second control node, the second end of the third transistor, the third end of the second transistor, the first end of the fourth transistor;

wherein the first end of the third transistor is connected to the high voltage; and

the third end of the third transistor is connected to the second end of the eighth transistor and the second end of the tenth transistor;

wherein the second end of the fourth transistor is connected to the low voltage; and

the third end of the fourth transistor is connected to the first control node, the second end of the first transistor, the first end of the second transistor, the first end of the seventh transistor, and the first end of the ninth transistor;

wherein the third end of the seventh transistor is connected to the first input signal line; and

the second end of the seventh transistor is connected to the second control signal line and the third end of the eighth transistor;

wherein the first end of the eighth transistor is connected to the fourth control signal;

wherein the third end of the ninth transistor is connected to the second input signal; and

the second end of the ninth transistor is connected to the third control signal and the third end of the tenth transistor;

wherein the first end of the tenth transistor is connected to the fifth control signal.

11. The driver circuit as claimed in claim 10, wherein the control circuit further comprises a first capacitor between the third end of the fourth transistor, and a second capacitor between the third end of the auxiliary transistor and the low voltage.

12. The driver circuit as claimed in claim 9, wherein at least one of the seventh transistor and the ninth transistor comprises an oxide semiconductor layer.