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Integrated level translator

  • US 10,395,700 B1
  • Filed: 03/20/2018
  • Issued: 08/27/2019
  • Est. Priority Date: 03/20/2018
  • Status: Active Grant
First Claim
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1. An integrated level translator circuit structure comprising:

  • a first PMOS transistor and second PMOS transistor each including a gate, a source and a drain;

    wherein the sources of the first and second PMOS transistor are coupled to a first voltage source, the gate of the first PMOS transistor is cross coupled to the drain of the second PMOS transistor, the gate of the second PMOS transistor is cross coupled to the drain of the first PMOS transistor, the drain of the first PMOS transistor is coupled to a first bit-line node, and wherein the drain of the second PMOS transistor is coupled to a second bit-line node;

    a write bit-switch having a first NMOS transistor coupled to the first bit-line node and a second NMOS transistor coupled to the second bit-line node, wherein the first and second NMOS transistors of the write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and

    a write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and a ground.

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