Integrated level translator

• US 10,395,700 B1
• Filed: 03/20/2018
• Issued: 08/27/2019
• Est. Priority Date: 03/20/2018
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bringivijayaraghavan, Venkatraghavan, Kumar Vavilla, Sreenivasa Chaitanya
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/926,272
• Time in Patent Office: 525 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments of the present disclosure provide a circuit structure including: first PMOS and second PMOS each including a gate, source, and drain; wherein sources of first and second PMOS are coupled to first voltage source, gate of first PMOS is cross coupled to drain of second PMOS, gate of second PMOS is cross coupled to drain of first PMOS, drain of the first PMOS is coupled to first bit-line node, and wherein drain of second PMOS is coupled to second bit-line node; write bit-switch having first NMOS coupled to first bit-line node and second NMOS coupled to second bit-line node, wherein first and second NMOS of write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and ground.

Claims

1. An integrated level translator circuit structure comprising:

a first PMOS transistor and second PMOS transistor each including a gate, a source and a drain;

wherein the sources of the first and second PMOS transistor are coupled to a first voltage source, the gate of the first PMOS transistor is cross coupled to the drain of the second PMOS transistor, the gate of the second PMOS transistor is cross coupled to the drain of the first PMOS transistor, the drain of the first PMOS transistor is coupled to a first bit-line node, and wherein the drain of the second PMOS transistor is coupled to a second bit-line node;

a write bit-switch having a first NMOS transistor coupled to the first bit-line node and a second NMOS transistor coupled to the second bit-line node, wherein the first and second NMOS transistors of the write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and

a write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and a ground.

2. The circuit structure of claim 1, wherein one of the pair of transistor stacks includes third NMOS transistor, a fifth NMOS transistor, and a first supply PMOS transistor, each of the third and fifth NMOS transistors and first supply PMOS transistor including a gate, a source, and a drain, the drain of the third NMOS transistor is coupled to a driver node, and the driver node is coupled to the source of the fifth NMOS transistor, and wherein the drain of the first supply PMOS transistor is coupled to the drain of the fifth NMOS transistor.

3. The circuit structure of claim 2, wherein the first supply PMOS transistor and the third NMOS transistor of the pair of NMOS transistors of the first transistor stack are configured to receive a first input signal from one of the pair of data inputs.

4. The circuit structure of claim 1, wherein the first bit-line node and second bit-line node are configured to receive a first bit-line input and a second bit-line input, respectively.

5. The circuit structure of claim 1, further comprising a first input PMOS transistor, having a gate, a source, and a drain, wherein the source of the first input PMOS transistor is coupled to the first bit-line node.

6. The circuit structure of claim 5, wherein the gate of the first input PMOS transistor is configured to receive a first control signal.

7. An integrated level translator circuit structure comprising:

a first PMOS transistor and a second PMOS transistor each including a gate, a source and a drain;

wherein the sources of the first and second PMOS transistors are coupled to a first voltage source, the gate of the first PMOS transistor is cross coupled to the drain of the second PMOS transistor, the gate of the second PMOS transistor is cross coupled to the drain of the first PMOS transistor, the drain of the first PMOS transistor is coupled to a first bit-line node, and wherein the drain of the second PMOS transistor is coupled to a second bit-line node;

a write bit-switch having a first NMOS transistor coupled to the first bit-line node and a second NMOS transistor coupled to the second bit-line node, wherein the first and second NMOS transistors of the write bit-switch are coupled to a first and second data node, respectively, and wherein the first and second data node are configured to receive a pair of data inputs; and

a write driver having a third NMOS transistor and fourth NMOS transistor, each of the third and fourth NMOS transistors including a gate, a source and a drain, wherein the sources of the third and fourth NMOS transistors are coupled to a ground, wherein the drains of the third and fourth NMOS transistors are coupled to the first and second data nodes respectively.

8. The circuit structure of claim 7, wherein the first bit-line node and second bit-line node are configured to receive a first bit-line input and a second bit-line input, respectively.

9. The circuit structure of claim 7, further comprising a first input PMOS transistor coupled to the first bit-line node.

10. The circuit structure of claim 9, wherein the first input PMOS transistor includes a gate coupled to a second control signal.

11. The circuit structure of claim 7, wherein the gates of the third and fourth NMOS transistor are configured to receive input signals.

12. The circuit structure of claim 7, wherein the pair of data inputs comprises at least two distinct data inputs.

13. A write driver and bitswitch circuit structure with a level translator, the structure comprising:

a first PMOS transistor and a second PMOS transistor each including a gate, a source and a drain;

wherein the sources of the first and second PMOS transistor source are coupled to a first voltage source, the gate of the first PMOS transistor is cross coupled to the drain of the second PMOS transistor, the gate of the second PMOS transistor is cross coupled to the drain of the first PMOS transistor, the drain of the first PMOS transistor is coupled to a first bit-line node, and wherein the drain of the second PMOS transistor is coupled to a second bit-line node;

a write bit-switch having a first NMOS transistor coupled to the first bit-line node and a second NMOS transistor coupled to the second bit-line node, wherein the first and second NMOS transistors of the write bit-switch are coupled to a first and second data node, respectively, and wherein the first and second data node are configured to receive a pair of data inputs; and

a write driver, further including;

a first transistor stack, having a third NMOS transistor, a fifth NMOS transistor, a first supply PMOS transistor, each of the third and fifth NMOS transistors and first supply PMOS transistor including a gate, a source, and a drain, wherein the drain of the third NMOS transistor is coupled to the source of the fifth NMOS transistor, and the drain of the first supply PMOS transistor is coupled to the drain of the fifth NMOS transistor, wherein the drain of the third NMOS transistor is coupled to the first data node; and

a second transistor stack, having a fourth NMOS transistor, a sixth NMOS transistor, a second supply PMOS transistor, each of the fourth and sixth NMOS transistors, and second supply PMOS transistor including a gate, a source, and a drain, wherein the drain of the fourth NMOS transistor is coupled to the source of the sixth transistor, and the drain of the second supply PMOS transistor is coupled to the drain of the sixth NMOS transistor, wherein the drain of the fourth NMOS transistor is coupled to the second data node.

14. The circuit structure of claim 13, wherein the first bit-line node and second bit-line node are configured to receive a first bit-line input and a second bit-line input, respectively.

15. The circuit structure of claim 14, further comprising a first input PMOS transistor having a gate, a source, and a drain, wherein the source of the first input PMOS transistor is coupled to the first bit-line node.

16. The circuit structure of claim 15, wherein the gate of the first input PMOS transistor is configured to receive a first control signal.

17. The circuit structure of claim 16, wherein the source from the third NMOS transistor and the source of the fourth NMOS transistor are coupled to a ground.

18. The circuit structure of claim 16, wherein the drain of the first supply PMOS transistor is coupled to a second voltage source.

19. The circuit structure of claim 18, wherein the first voltage source has a first voltage level and the second voltage source has a second voltage level, and wherein the first and second voltage levels are different.

20. The circuit structure of claim 13, wherein the fifth NMOS transistor is gated to a third voltage source.