Perpendicular source and bit lines for an MRAM array
First Claim
1. A memory device comprising:
- an array of memory cells wherein each memory cell comprises;
a respective magnetic random access memory (MRAM) element; and
a respective gating transistor;
a common wordline coupled to gates of gating transistors of said array of memory cells;
a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to a plurality of bit lines within said array of memory cells; and
said plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells, wherein, to store a data bit of a first logical value a voltage polarity of said common source line is held at a mid level voltage and an addressed bit line is asserted to ground and wherein, to store a data bit of a second logical value, said common source line is held to said mid level voltage and said addressed bit line is asserted at a voltage higher than said mid level voltage.
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Accused Products
Abstract
A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.
486 Citations
11 Claims
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1. A memory device comprising:
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an array of memory cells wherein each memory cell comprises; a respective magnetic random access memory (MRAM) element; and a respective gating transistor; a common wordline coupled to gates of gating transistors of said array of memory cells; a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to a plurality of bit lines within said array of memory cells; and said plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells, wherein, to store a data bit of a first logical value a voltage polarity of said common source line is held at a mid level voltage and an addressed bit line is asserted to ground and wherein, to store a data bit of a second logical value, said common source line is held to said mid level voltage and said addressed bit line is asserted at a voltage higher than said mid level voltage. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device comprising:
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an array of memory cells wherein each memory cell comprises; a respective magnetic random access memory (MRAM) element; and a respective gating transistor; a plurality of bit lines which are routed parallel to each other, wherein each bit line is associated with a respective memory cell of said array of memory cells; a common word line coupled to gates of gating transistors of said array of memory cells; and a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, wherein said array of memory cells is operable to store a data bit into an addressed memory cell of said array of memory cells responsive to a voltage applied between said common source line and an addressed bit line of said plurality of bit lines while said common word line is active, and wherein said addressed bit line is associated with said addressed memory cell, wherein, to store said data bit of a first logical value, a voltage polarity of said common source line is held at a mid level voltage and said addressed bit line is asserted to ground and wherein, to store said data bit of a second logical value, said common source line is held to said mid level voltage and said addressed bit line is asserted at a voltage hiqher than said mid level voltage. - View Dependent Claims (7)
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8. A method for programming a memory device,
said method comprising: -
selecting a bit line of a memory cell of an array; selecting a source line of the memory cell of the array, wherein the selected bit line and the selected source line are disposed perpendicularly to one another; driving a word line coupled to a gate of a gating transistor to activate the memory cell; wherein, to store a data bit of a first logical value, holding a voltage polarity of a common source line at a mid level voltage and asserting an addressed bit line to ground and wherein, to store a data bit of a second logical value, holding said common source line to said mid level voltage and asserting said addressed bit line at a voltage higher than said mid level voltage. - View Dependent Claims (9, 10, 11)
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Specification