Memory array with horizontal source line and sacrificial bitline per virtual source

• US 10,395,712 B2
• Filed: 12/28/2017
• Issued: 08/27/2019
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, El Baraji, Mourad, Crudele, Lester, Louie, Benjamin
• Primary Examiner(s): Mai, Son L
• Application Number:
  US15/857,264
• Publication Number:
  US 20190206473A1
• Time in Patent Office: 607 Days
• Field of Search: 365 51, 365158
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits

Abstract

A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.

Claims

1. A memory device comprising:

an array of memory cells wherein each memory cell comprises;

a respective magnetic random access memory (MRAM) element; and

a respective gating transistor;

a plurality of bit lines which are routed parallel to each other, wherein each bit line is associated with a respective memory cell of said array of memory cells;

a common wordline coupled to gates of gating transistors of said array of memory cells;

a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells; and

a sacrificial circuit element coupled to a sacrificial bit line, coupled to said common wordline and coupled to said common source line, wherein said sacrificial circuit element is operable to provide a desired voltage to said common source line wherein said desired voltage originates from said sacrificial bit line.

2. A memory device as described in claim 1 wherein said sacrificial circuit element comprises:

an MRAM cell which is shorted; and

a gating transistor.

3. A memory device as described in claim 1 wherein said sacrificial circuit element comprises a via element;

and a gating transistor.

4. A memory device as described in claim 1 wherein said sacrificial circuit element comprises a straight through connection;

and a gating transistor.

5. A memory device as described in claim 1 wherein said sacrificial bit line is parallel to said plurality of bit lines.

6. A memory device as described in claim 1 wherein said desired voltage on said common source line is operable to be used in conjunction with an active bit line of said plurality of bit lines to program a data value into an addressed memory cell of said memory array, wherein said addressed memory cell corresponds to said active bit line.

7. A memory device as described in claim 1 wherein each respective MRAM element of said memory array is coupled, at a first end thereof, to a respective bit line of said plurality of bit lines, and further coupled, at a second end thereof, to a drain of a respective gating transistor and wherein further said respective gating transistor comprises a gate coupled to said common wordline and a source coupled to said common source line.

8. A memory device as described in claim 1 wherein, an addressed memory cell, of said array of memory cells, is operable to be programmed with a data bit by:

making active said sacrificial bit line;

making active said wordline; and

making active a bit line, of said plurality of bit lines, that corresponds to said addressed memory cell while remainder bit lines of said plurality of bit lines remain inactive.

9. A memory array as described in claim 8 wherein a voltage polarity between said sacrificial bit line and said active bit line of said addressed memory cell define said data bit value.

10. A method of writing data to a memory device, said method comprising:

activating a common word line;

applying a first voltage to an addressed bit line of a plurality of bit lines; and

applying a second voltage to remainder bit lines of said plurality of bit lines, wherein a data bit value is stored into an addressed memory cell associated with said addressed bit line during a write cycle, and wherein further said memory device comprises;

an array of memory cells comprising said addressed memory cell, wherein each memory cell of said array of memory cells comprises;

a respective magnetic random access memory (MRAM) element; and

a respective gating transistor;

said plurality of bit lines routed parallel to each other, wherein each bit line is associated with a respective memory cell of said array of memory cells;

said common word line coupled to gates of gating transistors of said array of memory cells; and

said common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells

a sacrificial circuit element coupled to a sacrificial bit line, coupled to said common word line and coupled to said common source line, wherein said sacrificial circuit element is operable to provide a desired voltage to said common source line wherein said desired voltage originates from said sacrificial bit line.

11. A memory device as described in claim 10 wherein said sacrificial circuit element comprises:

an MRAM cell which is shorted; and

a gating transistor.

12. A memory device as described in claim 10 wherein said sacrificial circuit element comprises a via element;

and a gating transistor.

13. A memory device as described in claim 10 wherein said sacrificial circuit element comprises a straight through connection;

and a gating transistor.

14. A memory device as described in claim 10 wherein said sacrificial bit line is parallel to said plurality of bit lines.

15. A method as described in claim 10, wherein said memory device further comprises:

a first circuit for providing said first voltage on said addressed bit line of said plurality of bit lines during said write cycle; and

a second circuit for providing said second voltage on said remainder bit lines of said plurality of bit lines, wherein said second voltage is operable to be applied to said common source line, via said remainder bit lines, during said write cycle.

16. A method as described in claim 10 wherein said second voltage on said common source line is operable to be used in conjunction with said first voltage on said addressed bit line to store a data bit value into said addressed memory cell during said write cycle.

17. A method for programming a memory device comprising:

selecting a bit line of a memory cell of an array;

driving a word line coupled to a gate of a gating transistor to activate the memory cell, wherein unselected bit lines are grounded to a desired voltage, causing the desired voltage to bleed onto a common virtual source line of the cell, and wherein the selected bit line and the common source line are disposed perpendicularly to one another;

driving the selected bit line to a voltage higher than the desired voltage to program a first data value into the memory cell;

driving the selected bit line to a voltage lower than the desired voltage to program a second data value into the memory cell.

18. A method for programming a memory device as described in claim 17 wherein said desired voltage on said common source line is operable to be used in conjunction with an active bit line of said plurality of bit lines to program a data value into an addressed memory cell of said memory array, wherein said addressed memory cell corresponds to said active bit line.

19. A method for programming a memory device as described in claim 17 wherein said desired voltage on said common source line is ground, and wherein said active bit line is at a voltage lower than ground to program a data value into said addressed memory cell.

20. A method for programming a memory device as described in claim 17 wherein said desired voltage on said common source line is ground, and wherein said active bit line is at a voltage higher than ground to program a data value into said addressed memory cell.