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One-time programmable bitcell with native anti-fuse

  • US 10,395,745 B2
  • Filed: 10/23/2017
  • Issued: 08/27/2019
  • Est. Priority Date: 10/21/2016
  • Status: Active Grant
First Claim
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1. A one-time programmable memory device comprising:

  • a well region of a first polarity in a semiconductor substrate;

    a lightly-doped drain (LDD) region above a first portion of the well region, the LDD region having a second polarity that is opposite the first polarity and having a first doping concentration;

    a source region or a drain region of the second polarity above a second portion of the well region, the source region or the drain region having a second doping concentration that is higher than the first doping concentration, and a first breakdown voltage between the LDD region and the well region is higher than a second breakdown voltage between the source region or the drain region and the well region;

    a select device positioned at least in part above a portion of the source region or the drain region, the select device configured to form a channel between the source region or the drain region and the LDD region;

    an anti-fuse device positioned at least in part above a portion of the LDD region; and

    a shallow trench isolation (STI) region adjacent to the LDD region, wherein the LDD region extends underneath the anti-fuse device to the STI region.

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