Micro-transfer-printable flip-chip structures and methods

• US 10,395,966 B2
• Filed: 04/03/2018
• Issued: 08/27/2019
• Est. Priority Date: 11/15/2016
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Meitl, Matthew, Trindade, Antonio Jose Marques, Cok, Ronald S., Raymond, Brook, Prevatte, Carl
• Primary Examiner(s): Diallo, Mamadou L
• Application Number:
  US15/944,223
• Publication Number:
  US 20180226287A1
• Time in Patent Office: 511 Days
• CPC Class Codes: B65G 47/91 incorporating pneumatic, e.g. suction, grippers
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer. The support substrate is removed to expose the completed semiconductor device and, in some embodiments, a portion of the patterned release layer. In some embodiments, an entry path is formed to expose a portion of the patterned release layer. In some embodiments, the release layer is etched and the completed semiconductor devices transfer printed (e.g., micro-transfer printed) from the handle substrate to a destination substrate.

Claims

1. A method of making a semiconductor structure suitable for transfer printing, comprising:

providing a support substrate;

providing a semiconductor support layer over the support substrate;

providing a semiconductor layer disposed over the semiconductor support layer;

forming a plurality of semiconductor devices disposed in, on, or over the semiconductor support layer, each of the semiconductor devices comprising one or more electrical contacts exposed on a side of the semiconductor device opposite the semiconductor support layer;

forming a connection post on each of the exposed electrical contacts, the connection posts extending in a direction away from the semiconductor support layer;

patterning the semiconductor layer to separate the semiconductor devices in order to form a corresponding plurality of completed semiconductor devices;

patterning the semiconductor support layer to expose a portion of the support substrate;

forming a patterned release layer on or over the plurality of completed semiconductor devices, the patterned release layer (i) in contact with portions of the patterned semiconductor support layer on which the complete semiconductor devices are disposed and (ii) in contact with at least a portion of the support substrate;

providing a handle substrate;

disposing a conformable bonding layer on the patterned release layer or on the handle substrate;

bonding the handle substrate to the patterned release layer with the bonding layer; and

removing the support substrate to expose at least a portion of the patterned semiconductor support layer.

2. The method of claim 1, comprising:

disposing a capping layer over the patterned release layer, wherein the capping layer disperses, deflects, reflects, or absorbs a shock wave produced by laser ablation of at least a portion of the support substrate or semiconductor support layer.

3. The method of claim 1, comprising:

removing at least a portion of the patterned release layer to form a gap between at least a portion of the completed semiconductor device and at least a portion of the bonding layer; and

forming tethers physically connecting the plurality of completed semiconductor devices to anchors disposed on the handle substrate.

4. The method of claim 3, wherein the anchors are disposed laterally between ones of the plurality of completed semiconductor devices and each of the tethers extends laterally from one of the completed micro-device to one of the anchors.

5. The method of claim 3, wherein each of the tethers is a portion of the semiconductor support layer.

6. The method of claim 3, comprising micro-transfer printing the completed semiconductor devices from the handle substrate to a destination substrate and electrically contacting the connection posts to corresponding electrical contact pads on the destination substrate.

7. The method of claim 1, wherein removing the support substrate comprises one or more of laser liftoff, ablation, laser ablation, etching, and grinding.

8. The method of claim 1, wherein the semiconductor support layer is an ablation layer, a removal layer, or an etch-stop layer disposed between the completed semiconductor device and the support substrate.

9. The method of claim 1, wherein removing the support substrate comprises removing a removal layer.

10. A semiconductor structure suitable for transfer printing, comprising:

a handle substrate;

a bonding layer disposed in contact with the handle substrate;

a patterned release layer disposed in contact with the bonding layer;

a plurality of completed semiconductor devices disposed on or over the patterned release layer and each attached to one or more anchors disposed on the handle substrate with at least one tether, each of the plurality of completed semiconductor devices comprising at least one electrical contact disposed on a side of the completed semiconductor device between the completed semiconductor device and the handle substrate;

a connection post disposed on each of the at least one electrical contacts and extending from the electrical contact toward the handle substrate; and

a patterned semiconductor support layer comprising a surface on which is disposed the plurality of completed semiconductor devices and wherein the surface is in contact with a portion of the patterned release layer.

11. The semiconductor structure of claim 10, wherein a portion of the patterned release layer is exposed.

12. The semiconductor structure of claim 10, wherein a portion of the plurality of completed semiconductor devices or the semiconductor support layer is or comprises a removal layer.

13. The semiconductor structure of claim 10, comprising a support substrate in contact with the patterned semiconductor support layer and in contact with a portion of the patterned release layer.

14. The semiconductor structure of claim 12, wherein the support substrate comprises a removal layer.

15. The semiconductor structure of claim 10, wherein the patterned release layer defines a gap between the plurality of completed semiconductor devices and the bonding layer.

16. A semiconductor structure suitable for transfer printing, comprising:

a handle substrate;

a bonding layer disposed in contact with the handle substrate;

a capping layer disposed in contact with the bonding layer;

a patterned release layer disposed in contact with capping layer;

a plurality of completed semiconductor devices disposed on or over the patterned release layer and each attached to at least one anchor disposed on the handle substrate with at least one tether, each of the plurality of completed semiconductor devices comprising at least one electrical contact disposed on a side of the completed semiconductor device between the completed semiconductor device and the handle substrate;

a connection post disposed on each of the at least one electrical contacts and extending from the electrical contact toward the handle substrate; and

a patterned semiconductor support layer comprising a surface on which is disposed the completed semiconductor devices and wherein the surface is in contact with a portion of the patterned release layer.

17. The semiconductor structure of claim 16, wherein a portion of the patterned release layer is exposed.

18. The semiconductor structure of claim 16, wherein a portion of the plurality of completed semiconductor devices or the semiconductor support layer is a removal layer, or the semiconductor structure comprises a removal layer in contact with the completed semiconductor device.

19. The semiconductor structure of claim 16, comprising a support substrate in contact with the semiconductor support layer and in contact with a portion of the patterned release layer.

20. The semiconductor structure of claim 19, wherein the support substrate comprises a removal layer.