Dual trench structure

• US 10,395,970 B2
• Filed: 12/05/2013
• Issued: 08/27/2019
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Fadel, Maxim, Schoer, Gerrit
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US14/098,183
• Publication Number:
  US 20150162401A1
• Time in Patent Office: 2,091 Days
• Field of Search: 438430, 438435
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a dual trench structure. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method includes providing charge compensation trenches and termination trenches open to the top surface that are formed in a single etch step but with different final shield oxide thicknesses. A first shield oxide layer of a first thickness is formed on the plurality of charge compensation surfaces and the termination trench surface, wherein the first thickness of the first shield oxide layer is sufficient to allow formation of voids through the charge compensation trenches. Poly-silicon is deposited to form the electrodes in the charge compensation trenches. An isolated poly-silicon etch and clean etch is performed in the termination trenches to expose the first shield oxide layer. A second shield oxide layer is deposited on the first shield oxide layer in the termination trenches.

Claims

1. A method for fabricating a dual trench structure, comprising:

providing a wafer comprising a semiconductor layer including a top surface;

providing a plurality of charge compensation trenches open to said top surface and formed within said semiconductor layer, wherein said plurality of charge compensation trenches comprises a plurality of charge compensation trench surfaces;

forming a photoresist layer isolating said plurality of charge compensation trenches;

providing a termination trench open to said top surface and formed within said semiconductor layer, wherein said termination trench comprises a termination trench surface,

wherein said plurality of charge compensation trenches are formed to a depth less than a depth of said termination trench;

filling said plurality of charge compensation trenches and said termination trench with poly-silicon covering said first shield oxide layer; and

performing recess etch of said poly-silicon to below said top surface of said semiconductor layer;

forming a first shield oxide layer of a first predetermined thickness on said plurality of charge compensation trench surfaces and said termination trench surface;

forming a second shield oxide layer of a second predetermined thickness on said first shield oxide layer within said termination trench; and

forming a plurality of voids through centers of said plurality of charge compensation trenches during formation of said first shield oxide layer, wherein said first predetermined thickness of said first shield oxide layer is sufficient to allow formation of said voids.

2. The method of claim 1, further comprising:

etching poly-silicon from said termination trench to expose said first shield oxide layer of said first predetermined thickness.

3. The method of claim 2, further comprising:

stripping said photoresist layer; and

cleaning said termination trench to prepare additional oxide formation on said first shield oxide layer.

4. The method of claim 2, wherein said forming a second shield oxide layer comprises:

forming a second shield oxide layer over said first shield oxide layer that is exposed in said termination trench, wherein said first and second shield oxide layers formed in said termination trench comprise a second predetermined thickness sufficient to allow formation of another void in said termination trench, and wherein shield oxide of said first predetermined thickness in said plurality of charge compensation trenches is less thick than shield oxide of said second predetermined thickness in said termination trench.

5. The method of claim 4, further comprising:

filling said termination trench with poly-silicon doped covering said second shield oxide layer; and

performing an etch back of said poly-silicon in said termination trench below said top surface of said semiconductor layer.

6. The method of claim 5, further comprising:

performing a shield oxide layer refill of said termination trench; and

performing planarization to remove shield oxide down to approximately said top surface of said semiconductor layer while retaining a layer of said shield oxide over said poly-silicon filling said charge compensation trenches and said termination trench.

12. The method of claim 1 wherein said forming a second shield oxide layer takes place after said recess etch.

13. The method of claim 1 wherein said first shield oxide layer comprises tetraethyl orthosilicate oxide.

14. The method of claim 1 wherein said first shield oxide layer is formed by a deposition process.

15. The method of claim 1 wherein said second shield oxide layer is formed by a thermal oxidation process.

16. The method of claim 1 wherein said first and second shield oxide layers are of different composition.

7. A method for fabricating a dual trench structure, comprising:

simultaneously forming a plurality of charge compensation trenches and a termination trench in a semiconductor layer, wherein said plurality of charge compensation trenches is open to a top surface of said semiconductor layer, and wherein said termination trench is open to said top surface in said semiconductor layer;

oxidizing exposed surfaces of said plurality charge compensation trenches and said termination trench;

depositing a first shield oxide layer of a first predetermined thickness on said surfaces of said plurality of charge compensation trenches and said termination trench that are oxidized, wherein said first predetermined thickness of said first shield oxide layer is configured for formation of electrodes in said charge compensation trenches;

forming a second shield oxide layer of a second predetermined thickness on said first shield oxide layer within said termination trench; and

forming a plurality of voids through centers of said plurality of charge compensation trenches during formation of said first shield oxide layer, wherein said first predetermined thickness is configured to allow formation of said voids.

8. The method of claim 7, further comprising:

depositing poly-silicon over said first shield oxide layer and in said plurality of charge compensation trenches and said termination trench;

performing chemical-mechanical planarization (CMP) to remove poly-silicon until reaching said first shield oxide layer covering said top surface of said semiconductor layer; and

performing a recess etch of said poly-silicon below said top surface.

9. The method of claim 8, further comprising:

forming a photoresist layer isolating said plurality of charge compensation trenches;

dry etching poly-silicon from said termination trench to expose said first shield oxide layer of said first predetermined thickness;

stripping said photoresist layer;

conditioning exposed surfaces of said first shield oxide layer; and

wherein said forming a second shield oxide layer comprises depositing a second shield oxide layer over exposed surfaces of said first shield oxide layer to increase oxide thickness in said termination trench, wherein said first and second shield oxide layers comprise a second predetermined thickness configured for formation of electrodes in said termination trench.

10. The method of claim 9, further comprising:

avoiding use of a nitride hard mask to protect said termination trench to prepare said plurality of charge compensation trenches.

11. The method of claim 9, wherein said dry etching poly-silicon from said termination trench further comprises:

preserving oxide thickness of said first shield oxide layer at sidewalls and a bottom of said termination trench during over-etching.

17. A method for fabricating a dual trench structure, comprising:

providing a wafer comprising a semiconductor layer including a top surface;

providing a plurality of charge compensation trenches open to said top surface and formed within said semiconductor layer, wherein said plurality of charge compensation trenches comprises a plurality of charge compensation trench surfaces;

providing a termination trench open to said top surface and formed within said semiconductor layer, wherein said termination trench comprises a termination trench surface;

forming, by a deposition process, a first shield oxide layer of a first predetermined thickness on said plurality of charge compensation trench surfaces and said termination trench surface;

wherein said first shield oxide layer comprises tetraethyl orthosilicate oxide;

forming a second shield oxide layer of a second predetermined thickness on said first shield oxide layer within said termination trench; and

forming a plurality of voids through centers of said plurality of charge compensation trenches during formation of said first shield oxide layer, wherein said first predetermined thickness of said first shield oxide layer is sufficient to allow formation of said voids.