Three-dimensional semiconductor device and method of fabricating the same

• US 10,395,982 B2
• Filed: 11/07/2017
• Issued: 08/27/2019
• Est. Priority Date: 07/07/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Phil Ouk, Ahn, Jaeyoung, Lee, Sangsoo
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US15/805,560
• Publication Number:
  US 20190013237A1
• Time in Patent Office: 658 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.

Claims

1. A semiconductor device comprising:

a substrate including a first region and a second region;

a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;

an etch stop layer on the lower layer structure;

an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure;

a first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; and

a second contact plug filling a second opening, the upper layer structure and the etch stop layer including the second opening defined therethrough on the second region, a bottom surface of the first contact plug having a first distance from a bottom surface of the etch stop layer and a bottom surface of the second contact plug having a second distance from the bottom surface of the etch stop layer, the first distance being different from the second distance.

2. The semiconductor device of claim 1, wherein the second distance extends farther into the electrode layer of the lower layer structure from the bottom surface of the etch stop layer than the first distance.

3. The semiconductor device of claim 1, wherein the etch stop layer includes a material having the etch selectivity of about 1000:

1 or more with respect to both the upper layer structure and the lower layer structure.

4. The semiconductor device of claim 1, wherein the etch stop layer is an amorphous boron layer containing about 90 to 100 atomic percent of boron.

5. The semiconductor device of claim 1, wherein the first contact plug has a first sidewall portion facing the etch stop layer, the second contact plug has a second sidewall portion facing the etch stop layer, and the first sidewall portion has an inclined shape and the second sidewall portion has at least one of a substantially vertical shape or a rounded shape.

6. The semiconductor device of claim 1, wherein the upper layer structure includes at least one of a single insulation layer, a plurality of insulation layers, or a stack of conductive patterns and insulation layers.

7. A semiconductor device comprising:

a substrate including a first region and a second region;

a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;

an amorphous boron layer on the lower layer structure,

an upper layer structure on the amorphous boron layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the amorphous boron layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure;

a first contact plug filling a first opening, the upper layer structure and the amorphous boron layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; and

a second contact plug filling a second opening, the upper layer structure and the amorphous boron layer including the second opening defined therethrough on the second region, the second contact plug being in connection with the electrode layer of the lower layer structure,

wherein each of the first and second contact plugs includes an extended portion extending in a first direction perpendicular to a top surface of the substrate and a contacted portion protruding horizontally from the extended portion and disposed in the amorphous boron layer.

8. The semiconductor device of claim 7, wherein the amorphous boron layer includes about 90 to 100 atomic percent of boron.

9. The semiconductor device of claim 8, wherein the amorphous boron layer has the etch selectivity of about 1000:

1 or more with respect to both the lower layer structure and the upper layer structure.

10. The semiconductor device of claim 7, wherein a bottom surface of the first contact plug and a bottom surface of the second contact plug are at first and second distances, respectively, from a bottom surface of the amorphous boron layer, and the first and second distances are different from each other.

11. The semiconductor device of claim 10, wherein the second distance extends farther into the electrode layer of the lower layer structure from the bottom surface of the amorphous boron layer than the first distance.

12. The semiconductor device of claim 7, wherein the first contact plug has a first sidewall portion facing the amorphous boron layer, the second contact plug has a second sidewall portion facing the amorphous boron layer, and the first sidewall portion has an inclined shape and the second sidewall portion has at least one of a substantially vertical shape or a rounded shape.

13. The semiconductor device of claim 7, wherein at least one of the lower layer structure or the upper layer structure includes at least one of a single insulation layer, a plurality of insulation layers, or a stack of conductive patterns and insulation layers.

14. A three dimensional (3D) semiconductor memory device comprising:

a substrate including a cell array region and a connection region;

a stack structure on the substrate, the stack structure being an alternating structure of conductive layers and insulating layers, the stack structure having a stepped shape in the connection region, the stepped shape including a plurality of steps, the plurality of steps including at least a first step and a second step, the second step being lower than the first step, the first step and the second step each including a conductive layer at a top and an insulating layer under the conductive layer;

an etch stop layer on the stack structure;

a layer structure on the etch stop layer, a top surface of the layer structure being substantially a same level on the cell array region and the connection region, the etch stop layer having an etch selectivity with respect to both the layer structure and the stack structure;

a first contact plug filling a first opening, the layer structure and the etch stop layer including the first opening defined therethrough and reaching the conductive layer of the first step; and

a second contact plug filling a second opening, the layer structure and the etch stop layer including defined therethrough and reaching the conductive layer of the second step, a bottom surface of the first contact plug being farther into the conductive layer of the layer structure from a bottom surface of the etch stop layer than a bottom surface of the second contact plug.

15. The semiconductor memory device of claim 14, wherein the etch selectivity of the etch stop layer with respect to both the layer structure and the stack structure is about 1000:

1 or more.

16. The semiconductor memory device of claim 14, wherein the etch stop layer is an amorphous boron layer.

17. The semiconductor memory device of claim 16, wherein the amorphous boron layer includes about 90 to 100 atomic percent of boron.

18. The semiconductor memory device of claim 16, wherein the amorphous boron layer has the etch selectivity of about 1000:

1 or more with respect to both the layer structure and the stack structure.

19. The semiconductor memory device of claim 14, wherein the first contact plug has a first sidewall portion facing the etch stop layer, the second contact plug has a second sidewall portion facing the etch stop layer, and the first sidewall portion has an inclined shape, and the second sidewall portion has at least one of a substantially vertical shape or a rounded shape.

20. The semiconductor memory device of claim 14, wherein the layer structure includes at least one of a single insulation layer, a plurality of insulation layers, or a stack of conductive patterns and insulation layers.