Method for manufacturing oxide semiconductor device

• US 10,396,097 B2
• Filed: 10/06/2017
• Issued: 08/27/2019
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Ohara, Hiroki, Sasaki, Toshinari, Noda, Kosei, Kuwabara, Hideaki
• Primary Examiner(s): Yushin, Nikolay K
• Application Number:
  US15/726,691
• Publication Number:
  US 20180138211A1
• Time in Patent Office: 690 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Claims

1. A method for manufacturing a semiconductor device, the method comprising steps of:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a silicon oxide insulating layer over the oxide semiconductor layer;

forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers and in contact with a periphery of the oxide semiconductor layer and a first region of the oxide semiconductor layer;

forming a source electrode layer in contact with the oxide semiconductor layer through the first opening; and

forming a drain electrode layer in contact with the oxide semiconductor layer through the second opening,

wherein the first region of the oxide semiconductor layer comprises a channel formation region,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the gate electrode layer is a portion of a gate wiring layer,

wherein the source electrode layer is a portion of a source wiring layer, and

wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate wiring layer, the gate insulating layer, the silicon oxide insulating layer, and the source wiring layer are stacked in this order.

2. The method for manufacturing the semiconductor device according to claim 1,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the silicon oxide insulating layer interposed between the source electrode layer and the first end of the oxide semiconductor layer, and

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the silicon oxide insulating layer interposed between the drain electrode layer and the second end of the oxide semiconductor layer.

3. The method for manufacturing the semiconductor device according to claim 1, further comprising steps of:

forming a capacitor wiring in the same step as forming the gate electrode layer;

forming a dielectric over the capacitor wiring in the same step as forming the gate insulating layer; and

forming a capacitor electrode over the dielectric in the same step as forming the source electrode layer or the drain electrode layer.

4. The method for manufacturing the semiconductor device according to claim 1, wherein each of the first opening and the second opening completely overlaps with the oxide semiconductor layer.

5. The method for manufacturing the semiconductor device according to claim 1, wherein the oxide semiconductor layer completely overlaps with the gate electrode layer.

6. The method for manufacturing the semiconductor device according to claim 1, further comprising a step of performing a heat treatment on the oxide semiconductor layer at higher than or equal to 400°

C.

7. A method for manufacturing a semiconductor device, the method comprising steps of:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a silicon oxide insulating layer over the oxide semiconductor layer;

forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers and in contact with a periphery of the oxide semiconductor layer and a first region of the oxide semiconductor layer;

forming a source electrode layer in contact with the oxide semiconductor layer through the first opening;

forming a drain electrode layer in contact with the oxide semiconductor layer through the second opening;

forming an inorganic insulating film over the source electrode layer and the drain electrode layer;

forming a third opening in the inorganic insulating film; and

forming a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer through the third opening,

wherein the first region of the oxide semiconductor layer comprises a channel formation region,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the gate electrode layer is a portion of a gate wiring layer,

wherein the source electrode layer is a portion of a source wiring layer, and

wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate wiring layer, the gate insulating layer, the silicon oxide insulating layer, and the source wiring layer are stacked in this order.

8. The method for manufacturing the semiconductor device according to claim 7, wherein a plurality of slits are formed in the pixel electrode layer.

9. The method for manufacturing the semiconductor device according to claim 7,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the silicon oxide insulating layer interposed between the source electrode layer and the first end of the oxide semiconductor layer, and

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the silicon oxide insulating layer interposed between the drain electrode layer and the second end of the oxide semiconductor layer.

10. The method for manufacturing the semiconductor device according to claim 7, further comprising steps of:

forming a capacitor wiring in the same step as forming the gate electrode layer;

forming a dielectric over the capacitor wiring in the same step as forming the gate insulating layer; and

forming a capacitor electrode over the dielectric in the same step as forming the source electrode layer or the drain electrode layer.

11. The method for manufacturing the semiconductor device according to claim 7, wherein each of the first opening and the second opening completely overlaps with the oxide semiconductor layer.

12. The method for manufacturing the semiconductor device according to claim 7, wherein the oxide semiconductor layer completely overlaps with the gate electrode layer.

13. The method for manufacturing the semiconductor device according to claim 7, further comprising a step of performing a heat treatment on the oxide semiconductor layer at higher than or equal to 400°

C.

14. A method for manufacturing a semiconductor device, the method comprising steps of:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a semiconductor layer over the gate insulating layer;

forming a first insulating layer over the semiconductor layer;

forming a first opening and a second opening in the first insulating layer so that the first insulating layer covers and in contact with a periphery of the semiconductor layer and a first region of the semiconductor layer;

forming a source electrode layer to in contact with the semiconductor layer through the first opening; and

forming a drain electrode layer to in contact with the semiconductor layer through the second opening,

wherein the first region of the semiconductor layer comprises a channel formation region,

wherein the gate electrode layer is a portion of a gate wiring layer,

wherein the source electrode layer is a portion of a source wiring layer, and wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate wiring layer, the gate insulating layer, the first insulating layer, and the source wiring layer are stacked in this order.

15. The method for manufacturing the semiconductor device according to claim 14,

wherein the source electrode layer overlaps with a first end of the semiconductor layer with the first insulating layer interposed between the source electrode layer and the first end of the semiconductor layer, and

wherein the drain electrode layer overlaps with a second end of the semiconductor layer with the first insulating layer interposed between the drain electrode layer and the second end of the semiconductor layer.

16. The method for manufacturing the semiconductor device according to claim 14, further comprising steps of:

forming a capacitor wiring in the same step as forming the gate electrode layer;

forming a dielectric over the capacitor wiring in the same step as forming the gate insulating layer; and

forming a capacitor electrode over the dielectric in the same step as forming the source electrode layer or the drain electrode layer.

17. The method for manufacturing the semiconductor device according to claim 14, wherein each of the first opening and the second opening completely overlaps with the semiconductor layer.

18. The method for manufacturing the semiconductor device according to claim 14, wherein the semiconductor layer completely overlaps with the gate electrode layer.

19. The method for manufacturing the semiconductor device according to claim 14, further comprising a step of performing a heat treatment on the semiconductor layer at higher than or equal to 400°

C.