Method for FinFET LDD doping

• US 10,396,156 B2
• Filed: 01/29/2018
• Issued: 08/27/2019
• Est. Priority Date: 01/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chun Hsiung, Cheng, Ya-Yun, More, Shahaji B., Peng, Cheng-Yi, Lee, Wei-Yang, Yu, Kuo-Feng, Chen, Yen-Ming, Chen, Jian-Hao
• Primary Examiner(s): Ho, Hoang-Quan T
• Application Number:
  US15/882,285
• Publication Number:
  US 20190237543A1
• Time in Patent Office: 575 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.

Claims

1. A method, comprising:

providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;

performing a first implantation process to implant a dopant into the fin adjacent to the gate structure;

forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;

performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;

after the first etching process, performing a second implantation process to implant the dopant into the fin and the fin sidewall spacers;

after the second implantation process, performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers; and

epitaxially growing a semiconductor material in the trench.

2. The method of claim 1, wherein the first implantation process dopes the dopant into the fin up to a first depth, the portion of the fin above the fin sidewall spacers before the second etching process has a first height, and the first depth is about same as the first height.

3. The method of claim 1, wherein the first implantation process dopes the dopant into the fin up to a first depth, the first etching process reduces a height of the fin by a second depth, and the first depth is about same as the second depth.

4. The method of claim 1, wherein the fin has a first height, the first implantation process dopes the dopant into the fin up to a first depth, the fin sidewall spacers have a second height, and the second height is less than the first height minus the first depth.

5. The method of claim 4, wherein the second height is greater than or equal to the first height minus twice of the first depth.

6. The method of claim 1, wherein a height of the fin sidewall spacer is about 10 nm to about 25 nm during the second implantation process.

7. The method of claim 1, wherein the dopant includes a p-type dopant.

8. The method of claim 1, wherein the dopant includes an n-type dopant.

9. The method of claim 8, wherein the dopant includes phosphorus.

10. The method of claim 1, wherein the fin sidewall spacers include silicon nitride.

11. The method of claim 1, wherein the second implantation process is performed with a tilt angle of 0 to about 5 degrees.

12. A method, comprising:

providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;

first implanting a dopant into the fin, resulting in a doped upper portion of the fin;

forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin, wherein the fin sidewall spacers are below the doped upper portion of the fin;

first recessing the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;

second implanting the dopant into the fin and the fin sidewall spacers;

second recessing the fin adjacent to the gate sidewall spacers, resulting in a trench between the fin sidewall spacers; and

epitaxially growing a semiconductor material in the trench.

13. The method of claim 12, wherein a depth of the first recessing is about equal to a height of the doped upper portion of the fin.

14. The method of claim 12, wherein the second implanting of the dopant completely penetrates the portion of the fin above the fin sidewall spacers.

15. The method of claim 12, wherein the second implanting of the dopant completely penetrates the fin sidewall spacers.

16. The method of claim 12, wherein both the first and second implanting of the dopant are performed with a tilt angle about 5 degrees or less.

17. A method, comprising:

providing a structure that includes a substrate, an isolation structure over the substrate, a fin over the isolation structure and the substrate, and a gate structure engaging the fin;

first implanting a dopant into the fin, resulting in a doped upper portion of the fin;

after the first implanting, forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;

first recessing the fin adjacent to the gate sidewall spacers by a depth substantially equal to a height of the doped upper portion of the fin;

after the first recessing, second implanting the dopant into the fin and the fin sidewall spacers;

after the second implanting, second recessing the fin adjacent to the gate sidewall spacers, resulting in a trench between the fin sidewall spacers; and

epitaxially growing a semiconductor material in the trench.

18. The method of claim 17, wherein a bottom of the trench is above a top of the isolation structure.

19. The method of claim 17, wherein a bottom of the trench is below a top of the isolation structure.

20. The method of claim 17, further comprising:

forming offset spacers between the sidewalls of the gate structure and the gate sidewall spacers; and

forming offset spacers between the sidewalls of the fin and the fin sidewall spacers.