Semiconductor structure and manufacturing method thereof

• US 10,396,171 B2
• Filed: 11/01/2018
• Issued: 08/27/2019
• Est. Priority Date: 06/05/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liou, En-Chiuan, Tung, Yu-Cheng, Lee, Rung-Yuan, Yang, Chih-Wei
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US16/178,580
• Publication Number:
  US 20190081150A1
• Time in Patent Office: 299 Days
• Field of Search: None
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a substrate;

forming an interlayer dielectric (ILD) on the substrate;

forming a first dummy gate in the ILD, wherein the first dummy gate comprises a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively;

forming two contact holes in the ILD at two sides of the first dummy gate respectively;

removing the dummy gate electrode, so as to form a gate recess in the ILD;

filling a first material layer in the gate recess and a second material layer in the two contact holes respectively; and

performing an anneal process on the two spacers, to bend the two spacers into two inward curving spacers.

2. The method of claim 1, wherein the first material layer includes a spin-on dielectric (SOD) layer.

3. The method of claim 1, wherein the second material layer includes an advanced patterning film (APF).

4. The method of claim 1, further comprising removing the first material layer and the second material layer after the two inward curving spacers are formed.

5. The method of claim 4, further comprising forming a first gate dielectric layer and a first electrode between the two inward curving spacers, so as to form a first gate structure.

6. The method of claim 5, wherein the anneal process is performed after the first gate dielectric layer is formed.

7. The method of claim 5, wherein the first gate structure is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

8. The method of claim 4, further comprising forming a conductive layer in the two contact holes after the second material layer is removed.

9. The method of claim 1, further comprising forming a second gate structure, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode.

10. The method of claim 9, wherein the second gate structure is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

11. The method of claim 1, wherein each spacer is disposed between and directly contacts the first material layer and the second material layer.

12. The method of claim 1, wherein the anneal process is performed after the first material layer and the second material layer are formed.